mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-31 00:13:18 +00:00
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
This commit is contained in:
parent
fc0b5d5ab6
commit
915f4e34bf
2 changed files with 12 additions and 5 deletions
|
@ -52,7 +52,7 @@ module \$mul (A, B, Y);
|
|||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
generate
|
||||
if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
|
||||
if (A_SIGNED != B_SIGNED)
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
// NB: A_SIGNED == B_SIGNED from here
|
||||
else if (A_WIDTH < B_WIDTH)
|
||||
|
@ -103,10 +103,17 @@ module \$__mul (A, B, Y);
|
|||
|
||||
genvar i;
|
||||
generate
|
||||
if (A_WIDTH <= 1 || B_WIDTH <= 1)
|
||||
if (0) begin end
|
||||
`ifdef DSP_A_MINWIDTH
|
||||
else if (A_WIDTH < `DSP_A_MINWIDTH)
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
`ifdef DSP_MINWIDTH
|
||||
else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH)
|
||||
`endif
|
||||
`ifdef DSP_B_MINWIDTH
|
||||
else if (B_WIDTH < `DSP_B_MINWIDTH)
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
`endif
|
||||
`ifdef DSP_Y_MINWIDTH
|
||||
else if (Y_WIDTH < `DSP_Y_MINWIDTH)
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
`endif
|
||||
else if (A_WIDTH > `DSP_A_MAXWIDTH) begin
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue