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https://github.com/YosysHQ/yosys
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Added "connect" command
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Clifford Wolf
parent
67d155078d
commit
914e208aa3
2 changed files with 186 additions and 0 deletions
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@ -4,6 +4,7 @@ OBJS += passes/cmds/design.o
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OBJS += passes/cmds/select.o
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OBJS += passes/cmds/select.o
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OBJS += passes/cmds/show.o
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OBJS += passes/cmds/show.o
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OBJS += passes/cmds/rename.o
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OBJS += passes/cmds/rename.o
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OBJS += passes/cmds/connect.o
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OBJS += passes/cmds/scatter.o
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OBJS += passes/cmds/scatter.o
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OBJS += passes/cmds/splitnets.o
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OBJS += passes/cmds/splitnets.o
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OBJS += passes/cmds/stat.o
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OBJS += passes/cmds/stat.o
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185
passes/cmds/connect.cc
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185
passes/cmds/connect.cc
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@ -0,0 +1,185 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, RTLIL::SigSpec &sig)
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{
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CellTypes ct(design);
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RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID);
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for (auto &it : module->cells)
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for (auto &port : it.second->connections)
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if (ct.cell_output(it.second->type, port.first))
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sigmap(port.second).replace(sig, dummy_wire, &port.second);
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for (auto &conn : module->connections)
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sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
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}
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struct ConnectPass : public Pass {
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ConnectPass() : Pass("connect", "create or remove connections") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
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log("\n");
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log("Create a connection. This is equivialent to adding the statement 'assign\n");
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log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n");
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log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
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log("the -nounset option.\n");
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log("\n");
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log("\n");
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log(" connect [-nomap] -unset <expr>\n");
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log("\n");
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log("Unconnect all existing drivers for the specified expression.\n");
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log("\n");
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log("\n");
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log(" connect [-nomap] -port <cell> <port> <expr>\n");
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log("\n");
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log("Connect the specified cell port to the specified cell port.\n");
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log("\n");
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log("\n");
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log("Per default signal alias names are resolved and all signal names are mapped\n");
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log("the the signal name of the primary driver. Using the -nomap option deactivates\n");
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log("this behavior.\n");
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log("\n");
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log("The connect command operates in one module only. Either only one module must\n");
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log("be selected or an active module must be set using the 'cd' command.\n");
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log("\n");
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log("This command does not operate on module with processes.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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RTLIL::Module *module = NULL;
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for (auto &it : design->modules) {
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if (!design->selected(it.second))
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continue;
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if (module != NULL)
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log_cmd_error("Multiple modules selected: %s, %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.first));
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module = it.second;
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}
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if (module == NULL)
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log_cmd_error("No modules selected.\n");
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if (!module->processes.empty())
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log_cmd_error("Found processes in selected module.\n");
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bool flag_nounset = false, flag_nomap = false;
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std::string set_lhs, set_rhs, unset_expr;
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std::string port_cell, port_port, port_expr;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-nounset") {
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flag_nounset = true;
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continue;
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}
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if (arg == "-nomap") {
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flag_nomap = true;
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continue;
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}
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if (arg == "-set" && argidx+2 < args.size()) {
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set_lhs = args[++argidx];
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set_rhs = args[++argidx];
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continue;
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}
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if (arg == "-unset" && argidx+1 < args.size()) {
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unset_expr = args[++argidx];
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continue;
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}
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if (arg == "-port" && argidx+3 < args.size()) {
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port_cell = args[++argidx];
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port_port = args[++argidx];
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port_expr = args[++argidx];
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continue;
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}
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break;
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}
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SigMap sigmap;
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if (!flag_nomap)
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for (auto &it : module->connections) {
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std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
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std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
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for (size_t i = 0; i < lhs.size(); i++)
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if (rhs[i].wire != NULL)
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sigmap.add(lhs[i], rhs[i]);
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}
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if (!set_lhs.empty())
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{
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if (!unset_expr.empty() || !port_cell.empty())
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log_cmd_error("Cant use -set together with -unset and/or -port.\n");
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RTLIL::SigSpec sig_lhs, sig_rhs;
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if (!RTLIL::SigSpec::parse(sig_lhs, module, set_lhs))
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log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str());
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if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs))
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log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str());
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sigmap.apply(sig_lhs);
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sigmap.apply(sig_rhs);
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if (!flag_nounset)
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unset_drivers(design, module, sigmap, sig_lhs);
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module->connections.push_back(RTLIL::SigSig(sig_lhs, sig_rhs));
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}
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else
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if (!unset_expr.empty())
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{
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if (!port_cell.empty() || flag_nounset)
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log_cmd_error("Cant use -unset together with -port and/or -nounset.\n");
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RTLIL::SigSpec sig;
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if (!RTLIL::SigSpec::parse(sig, module, unset_expr))
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log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str());
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sigmap.apply(sig);
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unset_drivers(design, module, sigmap, sig);
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}
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else
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if (!port_cell.empty())
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{
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if (flag_nounset)
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log_cmd_error("Cant use -port together with -nounset.\n");
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if (module->cells.count(RTLIL::escape_id(port_cell)) == 0)
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log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
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RTLIL::SigSpec sig;
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if (!RTLIL::SigSpec::parse(sig, module, port_expr))
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log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
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module->cells.at(RTLIL::escape_id(port_cell))->connections[RTLIL::escape_id(port_port)] = sigmap(sig);
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}
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else
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log_cmd_error("Expected -set, -unset, or -port.\n");
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}
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} ConnectPass;
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