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https://github.com/YosysHQ/yosys
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Update from master
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parent
6931a3a47d
commit
914074a07c
5 changed files with 59 additions and 64 deletions
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@ -130,10 +130,9 @@ struct JsonWriter
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f << stringf(" }");
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f << stringf(" }");
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first = false;
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first = false;
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}
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}
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f << stringf("\n }");
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f << stringf("\n },\n");
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if (!module->get_blackbox_attribute()) {
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f << stringf(" \"cells\": {");
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f << stringf(",\n \"cells\": {");
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first = true;
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first = true;
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for (auto c : module->cells()) {
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for (auto c : module->cells()) {
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if (use_selection && !module->selected(c))
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if (use_selection && !module->selected(c))
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@ -196,9 +195,7 @@ struct JsonWriter
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f << stringf(" }");
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f << stringf(" }");
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first = false;
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first = false;
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}
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}
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f << stringf("\n }");
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f << stringf("\n }\n");
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}
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f << stringf("\n");
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f << stringf(" }");
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f << stringf(" }");
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}
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}
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@ -453,7 +453,7 @@ Aig::Aig(Cell *cell)
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int B = mk.inport("\\B");
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int B = mk.inport("\\B");
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int C = mk.inport("\\C");
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int C = mk.inport("\\C");
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int D = mk.inport("\\D");
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int D = mk.inport("\\D");
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int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D));
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int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
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mk.outport(Y, "\\Y");
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mk.outport(Y, "\\Y");
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goto optimize;
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goto optimize;
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}
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}
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@ -469,7 +469,7 @@ struct CellTypes
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if (cell->type == "$_AOI4_")
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if (cell->type == "$_AOI4_")
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return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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if (cell->type == "$_OAI4_")
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if (cell->type == "$_OAI4_")
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
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log_assert(arg4.bits.size() == 0);
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log_assert(arg4.bits.size() == 0);
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return eval(cell, arg1, arg2, arg3, errp);
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return eval(cell, arg1, arg2, arg3, errp);
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@ -465,12 +465,10 @@ struct WreduceWorker
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SigSpec initsig = init_attr_sigmap(w);
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SigSpec initsig = init_attr_sigmap(w);
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int width = std::min(GetSize(initval), GetSize(initsig));
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int width = std::min(GetSize(initval), GetSize(initsig));
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for (int i = 0; i < width; i++) {
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for (int i = 0; i < width; i++) {
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log_dump(initsig[i], remove_init_bits.count(initsig[i]));
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if (!remove_init_bits.count(initsig[i]))
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if (!remove_init_bits.count(initsig[i]))
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new_initval[i] = initval[i];
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new_initval[i] = initval[i];
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}
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}
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w->attributes.at("\\init") = new_initval;
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w->attributes.at("\\init") = new_initval;
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log_dump(w->name, initval, new_initval);
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}
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}
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}
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}
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}
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}
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@ -42,7 +42,7 @@ struct dff_map_bit_info_t {
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bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
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bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
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{
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{
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if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name))
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if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
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return false;
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return false;
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if (wire->port_input)
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if (wire->port_input)
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return false;
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return false;
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