mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
This commit is contained in:
Clifford Wolf
commit
913659d644
10 changed files with 458 additions and 10 deletions
|
|
@ -1,7 +1,17 @@
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|||
|
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OBJS += techlibs/gowin/synth_gowin.o
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OBJS += techlibs/gowin/determine_init.o
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||||
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||||
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt))
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|
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|
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh))
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|
|
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29
techlibs/gowin/bram.txt
Normal file
29
techlibs/gowin/bram.txt
Normal file
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@ -0,0 +1,29 @@
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bram $__GW1NR_SDP
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# uncomment when done
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# init 1
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abits 10 @a10d18
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dbits 16 @a10d18
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abits 11 @a11d9
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dbits 8 @a11d9
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abits 12 @a12d4
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dbits 4 @a12d4
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 1 0
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enable 1 1 @a10d18
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enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__GW1NR_SDP
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min bits 2048
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min efficiency 5
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shuffle_enable B
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make_transp
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endmatch
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12
techlibs/gowin/brams_init3.vh
Normal file
12
techlibs/gowin/brams_init3.vh
Normal file
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@ -0,0 +1,12 @@
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localparam [15:0] INIT_0 = {
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INIT[ 60], INIT[ 56], INIT[ 52], INIT[ 48], INIT[ 44], INIT[ 40], INIT[ 36], INIT[ 32], INIT[ 28], INIT[ 24], INIT[ 20], INIT[ 16], INIT[ 12], INIT[ 8], INIT[ 4], INIT[ 0]
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};
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localparam [15:0] INIT_1 = {
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INIT[ 61], INIT[ 57], INIT[ 53], INIT[ 49], INIT[ 45], INIT[ 41], INIT[ 37], INIT[ 33], INIT[ 29], INIT[ 25], INIT[ 21], INIT[ 17], INIT[ 13], INIT[ 9], INIT[ 5], INIT[ 1]
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};
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localparam [15:0] INIT_2 = {
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INIT[ 62], INIT[ 58], INIT[ 54], INIT[ 50], INIT[ 46], INIT[ 42], INIT[ 38], INIT[ 34], INIT[ 30], INIT[ 26], INIT[ 22], INIT[ 18], INIT[ 14], INIT[ 10], INIT[ 6], INIT[ 2]
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};
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localparam [15:0] INIT_3 = {
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INIT[ 63], INIT[ 59], INIT[ 55], INIT[ 51], INIT[ 47], INIT[ 43], INIT[ 39], INIT[ 35], INIT[ 31], INIT[ 27], INIT[ 23], INIT[ 19], INIT[ 15], INIT[ 11], INIT[ 7], INIT[ 3]
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};
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103
techlibs/gowin/brams_map.v
Normal file
103
techlibs/gowin/brams_map.v
Normal file
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@ -0,0 +1,103 @@
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/* Semi Dual Port (SDP) memory have the following configurations:
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* Memory Config RAM(BIT) Port Mode Memory Depth Data Depth
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* ----------------|---------| ----------|--------------|------------|
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* B-SRAM_16K_SD1 16K 16Kx1 16,384 1
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* B-SRAM_8K_SD2 16K 8Kx2 8,192 2
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* B-SRAM_4K_SD4 16K 4Kx2 4,096 4
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*/
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module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 16;
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parameter CFG_ENABLE_A = 3;
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parameter [16383:0] INIT = 16384'hx;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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generate if (CFG_DBITS == 1) begin
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SDP #(
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.READ_MODE(0),
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.BIT_WIDTH_0(1),
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.BIT_WIDTH_1(1),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
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.WREB(1'b0), .CEB(B1EN),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
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);
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end else if (CFG_DBITS == 2) begin
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SDP #(
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.READ_MODE(0),
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.BIT_WIDTH_0(2),
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.BIT_WIDTH_1(2),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
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.WREB(1'b0), .CEB(B1EN),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
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);
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end else if (CFG_DBITS <= 4) begin
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SDP #(
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.READ_MODE(0),
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.BIT_WIDTH_0(4),
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.BIT_WIDTH_1(4),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0),
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.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
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);
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end else if (CFG_DBITS <= 8) begin
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SDP #(
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.READ_MODE(0),
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.BIT_WIDTH_0(8),
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.BIT_WIDTH_1(8),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
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.WREB(1'b0), .CEB(B1EN),
|
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
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||||
);
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end else if (CFG_DBITS <= 16) begin
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||||
SDP #(
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.READ_MODE(0),
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.BIT_WIDTH_0(16),
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.BIT_WIDTH_1(16),
|
||||
.BLK_SEL(3'b000),
|
||||
.RESET_MODE("SYNC")
|
||||
) _TECHMAP_REPLACE_ (
|
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.CLKA(CLK2), .CLKB(CLK3),
|
||||
.WREA(A1EN), .OCE(1'b0),
|
||||
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
|
||||
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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||||
.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
|
||||
);
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end else begin
|
||||
wire TECHMAP_FAIL = 1'b1;
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end endgenerate
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||||
|
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endmodule
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@ -1,5 +1,9 @@
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module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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|
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module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
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module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
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module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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|
|
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@ -38,6 +38,17 @@ module DFFN (output reg Q, input CLK, D);
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Q <= D;
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endmodule
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module DFFR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
|
||||
end
|
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endmodule // DFFR (positive clock edge; synchronous reset)
|
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module VCC(output V);
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assign V = 1;
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endmodule
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||||
|
|
@ -63,3 +74,126 @@ module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
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|||
assign {COUT, SUM} = CIN + I1 + I0;
|
||||
endmodule // alu
|
||||
|
||||
module RAM16S4 (DO, DI, AD, WRE, CLK);
|
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parameter WIDTH = 4;
|
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parameter INIT_0 = 16'h0000;
|
||||
parameter INIT_1 = 16'h0000;
|
||||
parameter INIT_2 = 16'h0000;
|
||||
parameter INIT_3 = 16'h0000;
|
||||
|
||||
input [WIDTH-1:0] AD;
|
||||
input [WIDTH-1:0] DI;
|
||||
output [WIDTH-1:0] DO;
|
||||
input CLK;
|
||||
input WRE;
|
||||
|
||||
reg [15:0] mem0, mem1, mem2, mem3;
|
||||
|
||||
initial begin
|
||||
mem0 = INIT_0;
|
||||
mem1 = INIT_1;
|
||||
mem2 = INIT_2;
|
||||
mem3 = INIT_3;
|
||||
end
|
||||
|
||||
assign DO[0] = mem0[AD];
|
||||
assign DO[1] = mem1[AD];
|
||||
assign DO[2] = mem2[AD];
|
||||
assign DO[3] = mem3[AD];
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (WRE) begin
|
||||
mem0[AD] <= DI[0];
|
||||
mem1[AD] <= DI[1];
|
||||
mem2[AD] <= DI[2];
|
||||
mem3[AD] <= DI[3];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // RAM16S4
|
||||
|
||||
|
||||
(* blackbox *)
|
||||
module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
|
||||
//1'b0: Bypass mode; 1'b1 Pipeline mode
|
||||
parameter READ_MODE = 1'b0;
|
||||
parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
|
||||
parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
|
||||
parameter BLK_SEL = 3'b000;
|
||||
parameter RESET_MODE = "SYNC";
|
||||
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
input CLKA, CEA, CLKB, CEB;
|
||||
input OCE; // clock enable of memory output register
|
||||
input RESETA, RESETB; // resets output registers, not memory contents
|
||||
input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
|
||||
input [13:0] ADA, ADB;
|
||||
input [31:0] DI;
|
||||
input [2:0] BLKSEL;
|
||||
output [31:0] DO;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
72
techlibs/gowin/determine_init.cc
Normal file
72
techlibs/gowin/determine_init.cc
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct DetermineInitPass : public Pass {
|
||||
DetermineInitPass() : Pass("determine_init", "Determine the init value of cells") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
log("\n");
|
||||
log(" determine_init [selection]\n");
|
||||
log("\n");
|
||||
log("Determine the init value of cells that doesn't allow unknown init value.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
Const determine_init(Const init)
|
||||
{
|
||||
for (int i = 0; i < GetSize(init); i++) {
|
||||
if (init[i] != State::S0 && init[i] != State::S1)
|
||||
init[i] = State::S0;
|
||||
}
|
||||
|
||||
return init;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing DETERMINE_INIT pass (determine init value for cells).\n");
|
||||
|
||||
extra_args(args, args.size(), design);
|
||||
|
||||
size_t cnt = 0;
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type == "\\RAM16S4")
|
||||
{
|
||||
cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));
|
||||
cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
|
||||
cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
|
||||
cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
|
||||
cnt++;
|
||||
}
|
||||
}
|
||||
}
|
||||
log_header(design, "Updated %lu cells with determined init value.\n", cnt);
|
||||
}
|
||||
} DetermineInitPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
17
techlibs/gowin/dram.txt
Normal file
17
techlibs/gowin/dram.txt
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
bram $__GW1NR_RAM16S4
|
||||
init 1
|
||||
abits 4
|
||||
dbits 4
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 1
|
||||
clocks 0 1
|
||||
clkpol 0 1
|
||||
endbram
|
||||
|
||||
match $__GW1NR_RAM16S4
|
||||
make_outreg
|
||||
min wports 1
|
||||
endmatch
|
||||
31
techlibs/gowin/drams_map.v
Normal file
31
techlibs/gowin/drams_map.v
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 4;
|
||||
parameter CFG_DBITS = 4;
|
||||
|
||||
parameter [63:0] INIT = 64'bx;
|
||||
input CLK1;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
`include "brams_init3.vh"
|
||||
|
||||
RAM16S4
|
||||
#(.INIT_0(INIT_0),
|
||||
.INIT_1(INIT_1),
|
||||
.INIT_2(INIT_2),
|
||||
.INIT_3(INIT_3))
|
||||
_TECHMAP_REPLACE_
|
||||
(.AD(B1ADDR),
|
||||
.DI(B1DATA),
|
||||
.DO(A1DATA),
|
||||
.CLK(CLK1),
|
||||
.WRE(B1EN));
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -49,9 +49,15 @@ struct SynthGowinPass : public ScriptPass
|
|||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -nodffe\n");
|
||||
log(" do not use flipflops with CE in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use BRAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nodram\n");
|
||||
log(" do not use distributed RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
|
|
@ -65,7 +71,7 @@ struct SynthGowinPass : public ScriptPass
|
|||
}
|
||||
|
||||
string top_opt, vout_file;
|
||||
bool retime, flatten, nobram;
|
||||
bool retime, nobram, nodram, flatten, nodffe;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
|
|
@ -74,6 +80,8 @@ struct SynthGowinPass : public ScriptPass
|
|||
retime = false;
|
||||
flatten = true;
|
||||
nobram = false;
|
||||
nodffe = false;
|
||||
nodram = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -108,6 +116,14 @@ struct SynthGowinPass : public ScriptPass
|
|||
nobram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodram") {
|
||||
nodram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodffe") {
|
||||
nodffe = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
|
|
@ -147,25 +163,43 @@ struct SynthGowinPass : public ScriptPass
|
|||
{
|
||||
run("synth -run coarse");
|
||||
}
|
||||
|
||||
if (!nobram && check_label("bram", "(skip if -nobram)"))
|
||||
{
|
||||
run("memory_bram -rules +/gowin/bram.txt");
|
||||
run("techmap -map +/gowin/brams_map.v");
|
||||
run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
|
||||
}
|
||||
|
||||
if (!nodram && check_label("dram", "(skip if -nodram)"))
|
||||
{
|
||||
run("memory_bram -rules +/gowin/dram.txt");
|
||||
run("techmap -map +/gowin/drams_map.v");
|
||||
run("determine_init");
|
||||
}
|
||||
|
||||
if (check_label("fine"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -undriven -fine");
|
||||
run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
|
||||
run("opt -fine");
|
||||
run("clean -purge");
|
||||
run("splitnets -ports");
|
||||
run("setundef -undriven -zero");
|
||||
run("techmap -map +/techmap.v");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
{
|
||||
run("dffsr2dff");
|
||||
run("dff2dffs");
|
||||
run("opt_clean");
|
||||
if (!nodffe)
|
||||
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
|
||||
run("techmap -map +/gowin/cells_map.v");
|
||||
run("opt_expr -mux_undef");
|
||||
run("simplemap");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
run("abc -lut 4");
|
||||
|
|
@ -176,8 +210,10 @@ struct SynthGowinPass : public ScriptPass
|
|||
{
|
||||
run("techmap -map +/gowin/cells_map.v");
|
||||
run("hilomap -hicell VCC V -locell GND G");
|
||||
run("iopadmap -inpad IBUF O:I -outpad OBUF I:O");
|
||||
run("clean -purge");
|
||||
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
|
||||
run("dffinit -ff DFF Q INIT");
|
||||
run("clean");
|
||||
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue