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celltypes: Reword synthesizable comment

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Don't mention verilog.
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Krystine Sherwin 2025-03-01 11:23:13 +13:00
parent 82ae46dfeb
commit 9117926157
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kernel/celltypes.h
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@ -34,7 +34,7 @@ struct CellType
bool is_evaluable = false; bool is_evaluable = false;
// Cell has no state; outputs are determined solely by inputs // Cell has no state; outputs are determined solely by inputs
bool is_combinatorial = false; bool is_combinatorial = false;
// Cell is able to be fully represented in the synthesizable subset of verilog // Cell is able to be synthesized
bool is_synthesizable = false; bool is_synthesizable = false;
// Cell is built-in memory logic, includes flip-flops and latches, but not complex // Cell is built-in memory logic, includes flip-flops and latches, but not complex
// cells like $mem // cells like $mem