Merge pull request #4881 from YosysHQ/pmgen-pass-restructure

Move passes out of the passes/pmgen folder

Makefile

@@ -652,6 +652,9 @@ OBJS += libs/fst/fastlz.o
 OBJS += libs/fst/lz4.o
 endif
 
+techlibs/%_pm.h: passes/pmgen/pmgen.py techlibs/%.pmg
+	$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(notdir $*) $(filter-out $<,$^)
+
 ifneq ($(SMALL),1)
 
 OBJS += libs/subcircuit/subcircuit.o

passes/opt/.gitignore

@@ -0,0 +1 @@
+/peepopt*_pm.h

passes/opt/Makefile.inc

@@ -22,4 +22,18 @@ OBJS += passes/opt/opt_lut_ins.o
 OBJS += passes/opt/opt_ffinv.o
 OBJS += passes/opt/pmux2shiftx.o
 OBJS += passes/opt/muxpack.o
+
+OBJS += passes/opt/peepopt.o
+GENFILES += passes/opt/peepopt_pm.h
+passes/opt/peepopt.o: passes/opt/peepopt_pm.h
+$(eval $(call add_extra_objs,passes/opt/peepopt_pm.h))
+
+PEEPOPT_PATTERN  = passes/opt/peepopt_shiftmul_right.pmg
+PEEPOPT_PATTERN += passes/opt/peepopt_shiftmul_left.pmg
+PEEPOPT_PATTERN += passes/opt/peepopt_shiftadd.pmg
+PEEPOPT_PATTERN += passes/opt/peepopt_muldiv.pmg
+PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
+
+passes/opt/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
+	$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
 endif

passes/opt/peepopt.cc

@@ -28,7 +28,7 @@ bool did_something;
 // scratchpad configurations for pmgen
 int shiftadd_max_ratio;
 
-#include "passes/pmgen/peepopt_pm.h"
+#include "passes/opt/peepopt_pm.h"
 
 struct PeepoptPass : public Pass {
 	PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }

passes/pmgen/Makefile.inc

@@ -1,70 +1,10 @@
-%_pm.h: passes/pmgen/pmgen.py %.pmg
+passes/pmgen/%_pm.h: passes/pmgen/pmgen.py passes/pmgen/%.pmg
-	$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^)
+	$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(notdir $*) $(filter-out $<,$^)
 
 # --------------------------------------
 
 OBJS += passes/pmgen/test_pmgen.o
 GENFILES += passes/pmgen/test_pmgen_pm.h
-passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h
+passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h techlibs/ice40/ice40_dsp_pm.h techlibs/xilinx/xilinx_srl_pm.h
 $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
 
-# --------------------------------------
-
-OBJS += passes/pmgen/ice40_dsp.o
-GENFILES += passes/pmgen/ice40_dsp_pm.h
-passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/ice40_dsp_pm.h))
-
-# --------------------------------------
-
-OBJS += passes/pmgen/ice40_wrapcarry.o
-GENFILES += passes/pmgen/ice40_wrapcarry_pm.h
-passes/pmgen/ice40_wrapcarry.o: passes/pmgen/ice40_wrapcarry_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/ice40_wrapcarry_pm.h))
-
-# --------------------------------------
-
-OBJS += passes/pmgen/xilinx_dsp.o
-GENFILES += passes/pmgen/xilinx_dsp_pm.h
-GENFILES += passes/pmgen/xilinx_dsp48a_pm.h
-GENFILES += passes/pmgen/xilinx_dsp_CREG_pm.h
-GENFILES += passes/pmgen/xilinx_dsp_cascade_pm.h
-passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp48a_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_CREG_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
-
-# --------------------------------------
-
-OBJS += passes/pmgen/microchip_dsp.o
-GENFILES += passes/pmgen/microchip_dsp_pm.h
-GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h
-GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h
-passes/pmgen/microchip_dsp.o: passes/pmgen/microchip_dsp_pm.h passes/pmgen/microchip_dsp_CREG_pm.h passes/pmgen/microchip_dsp_cascade_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_CREG_pm.h))
-$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_cascade_pm.h))
-
-# --------------------------------------
-
-OBJS += passes/pmgen/peepopt.o
-GENFILES += passes/pmgen/peepopt_pm.h
-passes/pmgen/peepopt.o: passes/pmgen/peepopt_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
-
-PEEPOPT_PATTERN  = passes/pmgen/peepopt_shiftmul_right.pmg
-PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg
-PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg
-PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
-PEEPOPT_PATTERN += passes/pmgen/peepopt_formal_clockgateff.pmg
-
-passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
-	$(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
-
-# --------------------------------------
-
-OBJS += passes/pmgen/xilinx_srl.o
-GENFILES += passes/pmgen/xilinx_srl_pm.h
-passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h))

passes/pmgen/README.md

@@ -22,7 +22,7 @@ list of cells from that module:
     foobar_pm pm(module, module->selected_cells());
 
 The caller must make sure that none of the cells in the 2nd argument are
-deleted for as long as the patter matcher instance is used.
+deleted for as long as the pattern matcher instance is used.
 
 At any time it is possible to disable cells, preventing them from showing
 up in any future matches:

passes/pmgen/test_pmgen.cc

@@ -24,8 +24,8 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 #include "passes/pmgen/test_pmgen_pm.h"
-#include "passes/pmgen/ice40_dsp_pm.h"
+#include "techlibs/ice40/ice40_dsp_pm.h"
-#include "passes/pmgen/xilinx_srl_pm.h"
+#include "techlibs/xilinx/xilinx_srl_pm.h"
 
 #include "generate.h"
 

techlibs/.gitignore

@@ -1 +1,2 @@
 blackbox.v
+*_pm.h

techlibs/ice40/Makefile.inc

@@ -14,3 +14,13 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/spram.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/spram_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
+
+OBJS += techlibs/ice40/ice40_dsp.o
+GENFILES += techlibs/ice40/ice40_dsp_pm.h
+techlibs/ice40/ice40_dsp.o: techlibs/ice40/ice40_dsp_pm.h
+$(eval $(call add_extra_objs,techlibs/ice40/ice40_dsp_pm.h))
+
+OBJS += techlibs/ice40/ice40_wrapcarry.o
+GENFILES += techlibs/ice40/ice40_wrapcarry_pm.h
+techlibs/ice40/ice40_wrapcarry.o: techlibs/ice40/ice40_wrapcarry_pm.h
+$(eval $(call add_extra_objs,techlibs/ice40/ice40_wrapcarry_pm.h))

techlibs/ice40/ice40_dsp.cc

@@ -23,7 +23,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "passes/pmgen/ice40_dsp_pm.h"
+#include "techlibs/ice40/ice40_dsp_pm.h"
 
 void create_ice40_dsp(ice40_dsp_pm &pm)
 {

techlibs/ice40/ice40_wrapcarry.cc

@@ -23,7 +23,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "passes/pmgen/ice40_wrapcarry_pm.h"
+#include "techlibs/ice40/ice40_wrapcarry_pm.h"
 
 void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
 {

techlibs/microchip/Makefile.inc

@@ -29,3 +29,12 @@ $(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
 $(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
+
+OBJS += techlibs/microchip/microchip_dsp.o
+GENFILES += techlibs/microchip/microchip_dsp_pm.h
+GENFILES += techlibs/microchip/microchip_dsp_CREG_pm.h
+GENFILES += techlibs/microchip/microchip_dsp_cascade_pm.h
+techlibs/microchip/microchip_dsp.o: techlibs/microchip/microchip_dsp_pm.h techlibs/microchip/microchip_dsp_CREG_pm.h techlibs/microchip/microchip_dsp_cascade_pm.h
+$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_pm.h))
+$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_CREG_pm.h))
+$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_cascade_pm.h))

techlibs/microchip/microchip_dsp.cc

@@ -23,9 +23,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "passes/pmgen/microchip_dsp_CREG_pm.h"
+#include "techlibs/microchip/microchip_dsp_CREG_pm.h"
-#include "passes/pmgen/microchip_dsp_cascade_pm.h"
+#include "techlibs/microchip/microchip_dsp_cascade_pm.h"
-#include "passes/pmgen/microchip_dsp_pm.h"
+#include "techlibs/microchip/microchip_dsp_pm.h"
 
 void microchip_dsp_pack(microchip_dsp_pm &pm)
 {

techlibs/xilinx/Makefile.inc

@@ -46,3 +46,19 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
 
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
+
+OBJS += techlibs/xilinx/xilinx_dsp.o
+GENFILES += techlibs/xilinx/xilinx_dsp_pm.h
+GENFILES += techlibs/xilinx/xilinx_dsp48a_pm.h
+GENFILES += techlibs/xilinx/xilinx_dsp_CREG_pm.h
+GENFILES += techlibs/xilinx/xilinx_dsp_cascade_pm.h
+techlibs/xilinx/xilinx_dsp.o: techlibs/xilinx/xilinx_dsp_pm.h techlibs/xilinx/xilinx_dsp48a_pm.h techlibs/xilinx/xilinx_dsp_CREG_pm.h techlibs/xilinx/xilinx_dsp_cascade_pm.h
+$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_pm.h))
+$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp48a_pm.h))
+$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_CREG_pm.h))
+$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_cascade_pm.h))
+
+OBJS += techlibs/xilinx/xilinx_srl.o
+GENFILES += techlibs/xilinx/xilinx_srl_pm.h
+techlibs/xilinx/xilinx_srl.o: techlibs/xilinx/xilinx_srl_pm.h
+$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_srl_pm.h))

techlibs/xilinx/xilinx_dsp.cc

@@ -25,10 +25,10 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "passes/pmgen/xilinx_dsp_pm.h"
+#include "techlibs/xilinx/xilinx_dsp_pm.h"
-#include "passes/pmgen/xilinx_dsp48a_pm.h"
+#include "techlibs/xilinx/xilinx_dsp48a_pm.h"
-#include "passes/pmgen/xilinx_dsp_CREG_pm.h"
+#include "techlibs/xilinx/xilinx_dsp_CREG_pm.h"
-#include "passes/pmgen/xilinx_dsp_cascade_pm.h"
+#include "techlibs/xilinx/xilinx_dsp_cascade_pm.h"
 
 static Cell* addDsp(Module *module) {
 	Cell *cell = module->addCell(NEW_ID, ID(DSP48E1));

techlibs/xilinx/xilinx_srl.cc

@@ -24,7 +24,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "passes/pmgen/xilinx_srl_pm.h"
+#include "techlibs/xilinx/xilinx_srl_pm.h"
 
 void run_fixed(xilinx_srl_pm &pm)
 {