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Moved simple xilinx counter sim example to subdir

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This commit is contained in:
Clifford Wolf 2013-10-27 09:30:17 +01:00
parent 02f321b6fc
commit 90b016716b
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12
techlibs/xilinx/counter.v
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@ -1,12 +0,0 @@
module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule