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Rename recover_reduce to extract_reduce, fix args handling

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This commit is contained in:
Clifford Wolf 2017-08-28 19:52:06 +02:00
parent 3aad3ed3da
commit 908f34aafc
2 changed files with 25 additions and 8 deletions
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2
passes/techmap/Makefile.inc
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@ -17,7 +17,7 @@ OBJS += passes/techmap/iopadmap.o
OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/hilomap.o
OBJS += passes/techmap/extract.o OBJS += passes/techmap/extract.o
OBJS += passes/techmap/extract_fa.o OBJS += passes/techmap/extract_fa.o
OBJS += passes/techmap/recover_reduce.o OBJS += passes/techmap/extract_reduce.o
OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/alumacc.o
OBJS += passes/techmap/dff2dffe.o OBJS += passes/techmap/dff2dffe.o
OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/dffinit.o

31
passes/techmap/recover_reduce.cc → passes/techmap/extract_reduce.cc
View file

@ -23,19 +23,21 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct RecoverReducePass : public Pass { struct ExtractReducePass : public Pass
{
enum GateType { enum GateType {
And, And,
Or, Or,
Xor Xor
}; };
RecoverReducePass() : Pass("recover_reduce", "converts gate chains into $reduce_* cells") { } ExtractReducePass() : Pass("extract_reduce", "converts gate chains into $reduce_* cells") { }
virtual void help() virtual void help()
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" recover_reduce\n"); log(" extract_reduce [selection]\n");
log("\n"); log("\n");
log("converts gate chains into $reduce_* cells\n"); log("converts gate chains into $reduce_* cells\n");
log("\n"); log("\n");
@ -43,13 +45,26 @@ struct RecoverReducePass : public Pass {
log("with their corresponding $reduce_* cells. Because this command only operates on\n"); log("with their corresponding $reduce_* cells. Because this command only operates on\n");
log("these cell types, it is recommended to map the design to only these cell types\n"); log("these cell types, it is recommended to map the design to only these cell types\n");
log("using the `abc -g` command. Note that, in some cases, it may be more effective\n"); log("using the `abc -g` command. Note that, in some cases, it may be more effective\n");
log("to map the design to only $_AND_ cells, run recover_reduce, map the remaining\n"); log("to map the design to only $_AND_ cells, run extract_reduce, map the remaining\n");
log("parts of the design to AND/OR/XOR cells, and run recover_reduce a second time.\n"); log("parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
(void)args; log_header(design, "Executing EXTRACT_REDUCE pass.\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
// if (args[argidx] == "-v") {
// verbose = true;
// continue;
// }
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
@ -216,7 +231,9 @@ struct RecoverReducePass : public Pass {
for (auto cell : consumed_cells) for (auto cell : consumed_cells)
module->remove(cell); module->remove(cell);
} }
log_pop();
} }
} RecoverReducePass; } ExtractReducePass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END