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https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
This commit is contained in:
Eddie Hung
commit
90750e43ef
2 changed files with 212 additions and 57 deletions
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@ -200,7 +200,7 @@ prep
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design -save gold
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techmap
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muxcover -mux4=0 -nodecode
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muxcover -mux4=99 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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@ -228,7 +228,7 @@ prep
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design -save gold
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techmap
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muxcover -mux8=0 -nodecode
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muxcover -mux8=99 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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@ -256,7 +256,7 @@ prep
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design -save gold
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techmap
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muxcover -mux8=0 -nodecode
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muxcover -mux8=299 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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@ -284,7 +284,7 @@ prep
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design -save gold
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techmap
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muxcover -mux16=0 -nodecode
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muxcover -mux16=99 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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@ -312,7 +312,7 @@ prep
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design -save gold
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techmap
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muxcover -mux16=0 -nodecode
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muxcover -mux16=299 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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@ -341,7 +341,7 @@ prep
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design -save gold
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techmap
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muxcover -mux16=0 -nodecode
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muxcover -mux16=699 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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@ -356,3 +356,155 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_5_1 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[4*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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wreduce
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opt -full
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techmap
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muxcover -mux8=350
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_5_1 (nodecode) :: https://github.com/YosysHQ/yosys/issues/1132
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design -load gold
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wreduce
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opt -full
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techmap
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muxcover -mux8=350 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_9_1 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[3] == 1'b0)
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if (s[2] == 1'b0)
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if (s[1] == 1'b0)
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if (s[0] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[0] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[0] == 1'b0)
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o <= i[4*W+:W];
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else
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o <= i[5*W+:W];
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else
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if (s[0] == 1'b0)
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o <= i[6*W+:W];
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else
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o <= i[7*W+:W];
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else
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if (s[2] == 1'b0)
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if (s[1] == 1'b0)
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if (s[0] == 1'b0)
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o <= i[8*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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wreduce
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opt -full
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techmap
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muxcover -mux16=750
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_9_1 (nodecode) :: https://github.com/YosysHQ/yosys/issues/1132
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design -load gold
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wreduce
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opt -full
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techmap
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muxcover -mux16=750 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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