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aiger2: Only fail for reachable undirected bufnorm helper cells

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The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.

Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.

With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
This commit is contained in:
Jannis Harder 2025-09-23 14:44:13 +02:00
parent 9396e5e5fe
commit 90669ab4eb
1 changed files with 9 additions and 1 deletions
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10
backends/aiger2/aiger.cc
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@ -105,6 +105,13 @@ struct Index {
if (allow_blackboxes) { if (allow_blackboxes) {
info.found_blackboxes.insert(cell); info.found_blackboxes.insert(cell);
} else { } else {
// Even if we don't allow blackboxes these might still be
// present outside of any traversed input cones, so we
// can't bail at this point. If they are hit by a traversal
// (which can only really happen with $tribuf not
// $connect), we can still detect this as an error later.
if (cell->type == ID($connect) || (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
continue;
if (!submodule || submodule->get_blackbox_attribute()) if (!submodule || submodule->get_blackbox_attribute())
log_error("Unsupported cell type: %s (%s in %s)\n", log_error("Unsupported cell type: %s (%s in %s)\n",
log_id(cell->type), log_id(cell), log_id(m)); log_id(cell->type), log_id(cell), log_id(m));
@ -483,7 +490,8 @@ struct Index {
{ {
Design *design = index.design; Design *design = index.design;
auto &minfo = leaf_minfo(index); auto &minfo = leaf_minfo(index);
log_assert(minfo.suboffsets.count(cell)); if (!minfo.suboffsets.count(cell))
log_error("Reached unsupport cell %s (%s in %s)\n", log_id(cell->type), log_id(cell), log_id(cell->module));
Module *def = design->module(cell->type); Module *def = design->module(cell->type);
log_assert(def); log_assert(def);
levels.push_back(Level(index.modules.at(def), cell)); levels.push_back(Level(index.modules.at(def), cell));