mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Improved handling of init values in opt_rmdff

Browse source 
based on a patch by Mingyu Gao, user gaomy3832 on github
This commit is contained in:
Clifford Wolf 2015-04-18 08:04:31 +02:00
parent 8cdbcf6859
commit 9041f34233
1 changed files with 9 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

20
passes/opt/opt_rmdff.cc
View file

@ -83,26 +83,24 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx); val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
} }
if (dff->type == "$dff" && mux_drivers.has(sig_d) && !has_init) { if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
std::set<RTLIL::Cell*> muxes; std::set<RTLIL::Cell*> muxes;
mux_drivers.find(sig_d, muxes); mux_drivers.find(sig_d, muxes);
for (auto mux : muxes) { for (auto mux : muxes) {
RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A")); RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B")); RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B"));
if (sig_a == sig_q && sig_b.is_fully_const()) { if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) {
RTLIL::SigSig conn(sig_q, sig_b); mod->connect(sig_q, sig_b);
mod->connect(conn);
goto delete_dff; goto delete_dff;
} }
if (sig_b == sig_q && sig_a.is_fully_const()) { if (sig_b == sig_q && sig_a.is_fully_const() && (!has_init || val_init == sig_a.as_const())) {
RTLIL::SigSig conn(sig_q, sig_a); mod->connect(sig_q, sig_a);
mod->connect(conn);
goto delete_dff; goto delete_dff;
} }
} }
} }
if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) { if (sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
if (val_rv.bits.size() == 0) if (val_rv.bits.size() == 0)
val_rv = val_init; val_rv = val_init;
RTLIL::SigSig conn(sig_q, val_rv); RTLIL::SigSig conn(sig_q, val_rv);
@ -110,7 +108,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
goto delete_dff; goto delete_dff;
} }
if (sig_d.is_fully_undef() && sig_r.size() && !has_init) { if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
RTLIL::SigSig conn(sig_q, val_rv); RTLIL::SigSig conn(sig_q, val_rv);
mod->connect(conn); mod->connect(conn);
goto delete_dff; goto delete_dff;
@ -122,13 +120,13 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
goto delete_dff; goto delete_dff;
} }
if (sig_d.is_fully_const() && !sig_r.size() && !has_init) { if (sig_d.is_fully_const() && !sig_r.size() && (!has_init || val_init == sig_d.as_const())) {
RTLIL::SigSig conn(sig_q, sig_d); RTLIL::SigSig conn(sig_q, sig_d);
mod->connect(conn); mod->connect(conn);
goto delete_dff; goto delete_dff;
} }
if (sig_d == sig_q && !(sig_r.size() && has_init)) { if (sig_d == sig_q && (!sig_r.size() || !has_init || val_init == val_rv)) {
if (sig_r.size()) { if (sig_r.size()) {
RTLIL::SigSig conn(sig_q, val_rv); RTLIL::SigSig conn(sig_q, val_rv);
mod->connect(conn); mod->connect(conn);