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add tristate buffer and test

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This commit is contained in:
Pepijn de Vos 2019-10-28 15:18:01 +01:00
parent 9517525224
commit 903f997391
3 changed files with 21 additions and 2 deletions
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6
techlibs/gowin/cells_sim.v
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@ -302,6 +302,12 @@ module OBUF(output O, input I);
assign O = I; assign O = I;
endmodule endmodule
module TBUF (O, I, OEN);
input I, OEN;
output O;
assign O = OEN ? I : 1'bz;
endmodule
module GSR (input GSRI); module GSR (input GSRI);
wire GSRO = GSRI; wire GSRO = GSRI;
endmodule endmodule

2
techlibs/gowin/synth_gowin.cc
View file

@ -230,7 +230,7 @@ struct SynthGowinPass : public ScriptPass
run("techmap -map +/gowin/cells_map.v"); run("techmap -map +/gowin/cells_map.v");
run("setundef -undriven -params -zero"); run("setundef -undriven -params -zero");
run("hilomap -singleton -hicell VCC V -locell GND G"); run("hilomap -singleton -hicell VCC V -locell GND G");
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)");
run("dffinit -ff DFF Q INIT"); run("dffinit -ff DFF Q INIT");
run("clean"); run("clean");

13
tests/arch/gowin/tribuf.ys Normal file
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@ -0,0 +1,13 @@
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.
select -assert-count 1 t:TBUF
select -assert-count 2 t:IBUF
select -assert-none t:TBUF t:IBUF %% t:* %D