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add tristate buffer and test

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This commit is contained in:
Pepijn de Vos 2019-10-28 15:18:01 +01:00
parent 9517525224
commit 903f997391
3 changed files with 21 additions and 2 deletions
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6
techlibs/gowin/cells_sim.v
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@ -302,6 +302,12 @@ module OBUF(output O, input I);
assign O = I;
endmodule
module TBUF (O, I, OEN);
input I, OEN;
output O;
assign O = OEN ? I : 1'bz;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule