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	Update test too
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		|  | @ -13,8 +13,8 @@ read_verilog -formal <<EOT | ||||||
|     endmodule |     endmodule | ||||||
| EOT | EOT | ||||||
| 
 | 
 | ||||||
| script -select w:_RUNME* | script -scriptwire w:_RUNME* | ||||||
| 
 | 
 | ||||||
| select w:_DELETE | select w:_DELETE | ||||||
| script -select | script -scriptwire | ||||||
| select -assert-count 1 t:foo | select -assert-count 1 t:foo | ||||||
|  |  | ||||||
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