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Progress xsthammer scripts

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This commit is contained in:
Clifford Wolf 2013-06-10 16:17:09 +02:00
parent 7d790febb0
commit 9026511821
3 changed files with 37 additions and 27 deletions
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22
tests/xsthammer/run-check.sh
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@ -7,13 +7,17 @@ rm -rf check_temp
mkdir check_temp
cd check_temp
for job in $( ls ../rtl | sed 's,\.v$,,' )
if [ $# -eq 0 ]; then
set -- $( ls ../rtl | sed 's,\.v$,,' )
fi
for job
do
{
echo "module top(a, b, y1, y2);"
sed -r '/^(input|output) / !d; /output/ { s/ y;/ y1;/; p; }; s/ y1;/ y2;/;' ../rtl/$job.v
echo "${job}_rtl rtl_variant (.a(a), .b(b), .y(y1));"
echo "${job}_xst xst_variant (.a(a), .b(b), .y(y2));"
echo "module top(a, b, y_rtl, y_xst);"
sed -r '/^(input|output) / !d; /output/ { s/ y;/ y_rtl;/; p; }; s/ y_rtl;/ y_xst;/;' ../rtl/$job.v
echo "${job}_rtl rtl_variant (.a(a), .b(b), .y(y_rtl));"
echo "${job}_xst xst_variant (.a(a), .b(b), .y(y_xst));"
echo "endmodule"
} > ${job}_top.v
@ -23,6 +27,7 @@ do
echo "read_verilog ../rtl/$job.v"
echo "rename $job ${job}_rtl"
# echo "techmap ${job}_rtl"
echo "read_verilog ${job}_top.v"
echo "read_verilog ../xl_cells.v"
@ -37,17 +42,18 @@ do
{
echo "read_ilang ${job}_top.il"
echo "sat -verify -prove y1 y2 top"
echo "sat -verify -show a,b,y_rtl,y_xst -prove y_rtl y_xst top"
} > ${job}_cmp.ys
yosys ${job}_top.ys
../../../yosys ${job}_top.ys
if yosys -l ${job}.log ${job}_cmp.ys; then
if ../../../yosys -l ${job}.log ${job}_cmp.ys; then
mv ${job}.log ../check/${job}.log
rm -f ../check/${job}.err
else
mv ${job}.log ../check/${job}.err
rm -f ../check/${job}.log
# break
fi
done