diff --git a/kernel/ff.cc b/kernel/ff.cc
index 8b38b84cb..0826cb8d4 100644
--- a/kernel/ff.cc
+++ b/kernel/ff.cc
@@ -21,245 +21,316 @@
 
 USING_YOSYS_NAMESPACE
 
-FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initvals, cell_->name)
-{
-	cell = cell_;
-	sig_q = cell->getPort(ID::Q);
-	width = GetSize(sig_q);
-	attributes = cell->attributes;
+// sorry
+template<typename InputType, typename OutputType, typename = std::enable_if_t<std::is_base_of_v<FfTypeData, OutputType>>>
+void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
+	Cell* cell = nullptr;
+	IdString type;
+	constexpr bool have_cell = std::is_same_v<InputType, Cell*>;
+	if constexpr (std::is_same_v<InputType, IdString>) {
+		type = flop;
+	} else {
+		static_assert(std::is_same_v<InputType, Cell*>);
+		cell = flop;
+		type = flop->type;
+	}
+	if constexpr (have_cell) {
+		info.sig_q = cell->getPort(ID::Q);
+		info.width = GetSize(info.sig_q);
+		info.attributes = cell->attributes;
+		if (initvals)
+			info.val_init = (*initvals)(info.sig_q);
+	}
 
-	if (initvals)
-		val_init = (*initvals)(sig_q);
 
-	std::string type_str = cell->type.str();
+	std::string type_str = type.str();
 
-	if (cell->type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
-		if (cell->type.in(ID($anyinit), ID($ff))) {
-			has_gclk = true;
-			sig_d = cell->getPort(ID::D);
-			if (cell->type == ID($anyinit)) {
-				is_anyinit = true;
-				log_assert(val_init.is_fully_undef());
+	if (type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
+		if (type.in(ID($anyinit), ID($ff))) {
+			info.has_gclk = true;
+			if constexpr (have_cell)
+				info.sig_d = cell->getPort(ID::D);
+			if (type == ID($anyinit)) {
+				info.is_anyinit = true;
+				if constexpr (have_cell)
+					log_assert(info.val_init.is_fully_undef());
 			}
-		} else if (cell->type == ID($sr)) {
+		} else if (type == ID($sr)) {
 			// No data input at all.
-		} else if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
-			has_aload = true;
-			sig_aload = cell->getPort(ID::EN);
-			pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
-			sig_ad = cell->getPort(ID::D);
+		} else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
+			info.has_aload = true;
+			if constexpr (have_cell) {
+				info.sig_aload = cell->getPort(ID::EN);
+				info.pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
+				info.sig_ad = cell->getPort(ID::D);
+			}
 		} else {
-			has_clk = true;
-			sig_clk = cell->getPort(ID::CLK);
-			pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
-			sig_d = cell->getPort(ID::D);
+			info.has_clk = true;
+			if constexpr (have_cell) {
+				info.sig_clk = cell->getPort(ID::CLK);
+				info.pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
+				info.sig_d = cell->getPort(ID::D);
+			}
 		}
-		if (cell->type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
-			has_ce = true;
-			sig_ce = cell->getPort(ID::EN);
-			pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
+		if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
+			info.has_ce = true;
+			if constexpr (have_cell) {
+				info.sig_ce = cell->getPort(ID::EN);
+				info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
+			}
 		}
-		if (cell->type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
-			has_sr = true;
-			sig_clr = cell->getPort(ID::CLR);
-			sig_set = cell->getPort(ID::SET);
-			pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
-			pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
+		if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
+			info.has_sr = true;
+			if constexpr (have_cell) {
+				info.sig_clr = cell->getPort(ID::CLR);
+				info.sig_set = cell->getPort(ID::SET);
+				info.pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
+				info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
+			}
 		}
-		if (cell->type.in(ID($aldff), ID($aldffe))) {
-			has_aload = true;
-			sig_aload = cell->getPort(ID::ALOAD);
-			pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
-			sig_ad = cell->getPort(ID::AD);
+		if (type.in(ID($aldff), ID($aldffe))) {
+			info.has_aload = true;
+			if constexpr (have_cell) {
+				info.sig_aload = cell->getPort(ID::ALOAD);
+				info.pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
+				info.sig_ad = cell->getPort(ID::AD);
+			}
 		}
-		if (cell->type.in(ID($adff), ID($adffe), ID($adlatch))) {
-			has_arst = true;
-			sig_arst = cell->getPort(ID::ARST);
-			pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
-			val_arst = cell->getParam(ID::ARST_VALUE);
+		if (type.in(ID($adff), ID($adffe), ID($adlatch))) {
+			info.has_arst = true;
+			if constexpr (have_cell) {
+				info.sig_arst = cell->getPort(ID::ARST);
+				info.pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
+				info.val_arst = cell->getParam(ID::ARST_VALUE);
+			}
 		}
-		if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
-			has_srst = true;
-			sig_srst = cell->getPort(ID::SRST);
-			pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
-			val_srst = cell->getParam(ID::SRST_VALUE);
-			ce_over_srst = cell->type == ID($sdffce);
+		if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
+			info.has_srst = true;
+			if constexpr (have_cell) {
+				info.sig_srst = cell->getPort(ID::SRST);
+				info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
+				info.val_srst = cell->getParam(ID::SRST_VALUE);
+			}
+			info.ce_over_srst = type == ID($sdffce);
 		}
-	} else if (cell->type == ID($_FF_)) {
-		is_fine = true;
-		has_gclk = true;
-		sig_d = cell->getPort(ID::D);
+	} else if (type == ID($_FF_)) {
+		info.is_fine = true;
+		info.has_gclk = true;
+		if constexpr (have_cell)
+			info.sig_d = cell->getPort(ID::D);
 	} else if (type_str.substr(0, 5) == "$_SR_") {
-		is_fine = true;
-		has_sr = true;
-		pol_set = type_str[5] == 'P';
-		pol_clr = type_str[6] == 'P';
-		sig_set = cell->getPort(ID::S);
-		sig_clr = cell->getPort(ID::R);
+		info.is_fine = true;
+		info.has_sr = true;
+		info.pol_set = type_str[5] == 'P';
+		info.pol_clr = type_str[6] == 'P';
+		if constexpr (have_cell) {
+			info.sig_set = cell->getPort(ID::S);
+			info.sig_clr = cell->getPort(ID::R);
+		}
 	} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[6] == 'P';
-		sig_clk = cell->getPort(ID::C);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[6] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+		}
 	} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[7] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_ce = true;
-		pol_ce = type_str[8] == 'P';
-		sig_ce = cell->getPort(ID::E);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[7] == 'P';
+		info.has_ce = true;
+		info.pol_ce = type_str[8] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_ce = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[6] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_arst = true;
-		pol_arst = type_str[7] == 'P';
-		sig_arst = cell->getPort(ID::R);
-		val_arst = type_str[8] == '1' ? State::S1 : State::S0;
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[6] == 'P';
+		info.has_arst = true;
+		info.pol_arst = type_str[7] == 'P';
+		info.val_arst = type_str[8] == '1' ? State::S1 : State::S0;
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_arst = cell->getPort(ID::R);
+		}
 	} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[7] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_arst = true;
-		pol_arst = type_str[8] == 'P';
-		sig_arst = cell->getPort(ID::R);
-		val_arst = type_str[9] == '1' ? State::S1 : State::S0;
-		has_ce = true;
-		pol_ce = type_str[10] == 'P';
-		sig_ce = cell->getPort(ID::E);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[7] == 'P';
+		info.has_arst = true;
+		info.pol_arst = type_str[8] == 'P';
+		info.val_arst = type_str[9] == '1' ? State::S1 : State::S0;
+		info.has_ce = true;
+		info.pol_ce = type_str[10] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_arst = cell->getPort(ID::R);
+			info.sig_ce = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[8] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_aload = true;
-		pol_aload = type_str[9] == 'P';
-		sig_aload = cell->getPort(ID::L);
-		sig_ad = cell->getPort(ID::AD);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[8] == 'P';
+		info.has_aload = true;
+		info.pol_aload = type_str[9] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_aload = cell->getPort(ID::L);
+			info.sig_ad = cell->getPort(ID::AD);
+		}
 	} else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[9] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_aload = true;
-		pol_aload = type_str[10] == 'P';
-		sig_aload = cell->getPort(ID::L);
-		sig_ad = cell->getPort(ID::AD);
-		has_ce = true;
-		pol_ce = type_str[11] == 'P';
-		sig_ce = cell->getPort(ID::E);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[9] == 'P';
+		info.has_aload = true;
+		info.pol_aload = type_str[10] == 'P';
+		info.has_ce = true;
+		info.pol_ce = type_str[11] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_aload = cell->getPort(ID::L);
+			info.sig_ad = cell->getPort(ID::AD);
+			info.sig_ce = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[8] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_sr = true;
-		pol_set = type_str[9] == 'P';
-		pol_clr = type_str[10] == 'P';
-		sig_set = cell->getPort(ID::S);
-		sig_clr = cell->getPort(ID::R);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[8] == 'P';
+		info.has_sr = true;
+		info.pol_set = type_str[9] == 'P';
+		info.pol_clr = type_str[10] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_set = cell->getPort(ID::S);
+			info.sig_clr = cell->getPort(ID::R);
+		}
 	} else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[9] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_sr = true;
-		pol_set = type_str[10] == 'P';
-		pol_clr = type_str[11] == 'P';
-		sig_set = cell->getPort(ID::S);
-		sig_clr = cell->getPort(ID::R);
-		has_ce = true;
-		pol_ce = type_str[12] == 'P';
-		sig_ce = cell->getPort(ID::E);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[9] == 'P';
+		info.has_sr = true;
+		info.pol_set = type_str[10] == 'P';
+		info.pol_clr = type_str[11] == 'P';
+		info.has_ce = true;
+		info.pol_ce = type_str[12] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_set = cell->getPort(ID::S);
+			info.sig_clr = cell->getPort(ID::R);
+			info.sig_ce = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[7] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_srst = true;
-		pol_srst = type_str[8] == 'P';
-		sig_srst = cell->getPort(ID::R);
-		val_srst = type_str[9] == '1' ? State::S1 : State::S0;
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[7] == 'P';
+		info.has_srst = true;
+		info.pol_srst = type_str[8] == 'P';
+		info.val_srst = type_str[9] == '1' ? State::S1 : State::S0;
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_srst = cell->getPort(ID::R);
+		}
 	} else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[8] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_srst = true;
-		pol_srst = type_str[9] == 'P';
-		sig_srst = cell->getPort(ID::R);
-		val_srst = type_str[10] == '1' ? State::S1 : State::S0;
-		has_ce = true;
-		pol_ce = type_str[11] == 'P';
-		sig_ce = cell->getPort(ID::E);
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[8] == 'P';
+		info.has_srst = true;
+		info.pol_srst = type_str[9] == 'P';
+		info.val_srst = type_str[10] == '1' ? State::S1 : State::S0;
+		info.has_ce = true;
+		info.pol_ce = type_str[11] == 'P';
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_srst = cell->getPort(ID::R);
+			info.sig_ce = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
-		is_fine = true;
-		sig_d = cell->getPort(ID::D);
-		has_clk = true;
-		pol_clk = type_str[9] == 'P';
-		sig_clk = cell->getPort(ID::C);
-		has_srst = true;
-		pol_srst = type_str[10] == 'P';
-		sig_srst = cell->getPort(ID::R);
-		val_srst = type_str[11] == '1' ? State::S1 : State::S0;
-		has_ce = true;
-		pol_ce = type_str[12] == 'P';
-		sig_ce = cell->getPort(ID::E);
-		ce_over_srst = true;
+		info.is_fine = true;
+		info.has_clk = true;
+		info.pol_clk = type_str[9] == 'P';
+		info.has_srst = true;
+		info.pol_srst = type_str[10] == 'P';
+		info.val_srst = type_str[11] == '1' ? State::S1 : State::S0;
+		info.has_ce = true;
+		info.pol_ce = type_str[12] == 'P';
+		info.ce_over_srst = true;
+		if constexpr (have_cell) {
+			info.sig_d = cell->getPort(ID::D);
+			info.sig_clk = cell->getPort(ID::C);
+			info.sig_srst = cell->getPort(ID::R);
+			info.sig_ce = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
-		is_fine = true;
-		has_aload = true;
-		sig_ad = cell->getPort(ID::D);
-		has_aload = true;
-		pol_aload = type_str[9] == 'P';
-		sig_aload = cell->getPort(ID::E);
+		info.is_fine = true;
+		info.has_aload = true;
+		info.has_aload = true;
+		info.pol_aload = type_str[9] == 'P';
+		if constexpr (have_cell) {
+			info.sig_ad = cell->getPort(ID::D);
+			info.sig_aload = cell->getPort(ID::E);
+		}
 	} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
-		is_fine = true;
-		has_aload = true;
-		sig_ad = cell->getPort(ID::D);
-		has_aload = true;
-		pol_aload = type_str[9] == 'P';
-		sig_aload = cell->getPort(ID::E);
-		has_arst = true;
-		pol_arst = type_str[10] == 'P';
-		sig_arst = cell->getPort(ID::R);
-		val_arst = type_str[11] == '1' ? State::S1 : State::S0;
+		info.is_fine = true;
+		info.has_aload = true;
+		info.has_aload = true;
+		info.pol_aload = type_str[9] == 'P';
+		info.has_arst = true;
+		info.pol_arst = type_str[10] == 'P';
+		info.val_arst = type_str[11] == '1' ? State::S1 : State::S0;
+		if constexpr (have_cell) {
+			info.sig_ad = cell->getPort(ID::D);
+			info.sig_aload = cell->getPort(ID::E);
+			info.sig_arst = cell->getPort(ID::R);
+		}
 	} else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
-		is_fine = true;
-		has_aload = true;
-		sig_ad = cell->getPort(ID::D);
-		has_aload = true;
-		pol_aload = type_str[11] == 'P';
-		sig_aload = cell->getPort(ID::E);
-		has_sr = true;
-		pol_set = type_str[12] == 'P';
-		pol_clr = type_str[13] == 'P';
-		sig_set = cell->getPort(ID::S);
-		sig_clr = cell->getPort(ID::R);
+		info.is_fine = true;
+		info.has_aload = true;
+		info.has_aload = true;
+		info.pol_aload = type_str[11] == 'P';
+		info.has_sr = true;
+		info.pol_set = type_str[12] == 'P';
+		info.pol_clr = type_str[13] == 'P';
+		if constexpr (have_cell) {
+			info.sig_ad = cell->getPort(ID::D);
+			info.sig_aload = cell->getPort(ID::E);
+			info.sig_set = cell->getPort(ID::S);
+			info.sig_clr = cell->getPort(ID::R);
+		}
 	} else {
 		log_assert(0);
 	}
-	if (has_aload && !has_clk && !has_sr && !has_arst && sig_ad.is_fully_const()) {
-		// Plain D latches with const D treated specially.
-		has_aload = false;
-		has_arst = true;
-		sig_arst = sig_aload;
-		pol_arst = pol_aload;
-		val_arst = sig_ad.as_const();
-	}
+	if constexpr (have_cell)
+		if (info.has_aload && !info.has_clk && !info.has_sr && !info.has_arst && info.sig_ad.is_fully_const()) {
+			// Plain D latches with const D treated specially.
+			info.has_aload = false;
+			info.has_arst = true;
+			info.sig_arst = info.sig_aload;
+			info.pol_arst = info.pol_aload;
+			info.val_arst = info.sig_ad.as_const();
+		}
+}
+
+FfTypeData::FfTypeData(IdString type) : FfTypeData()
+{
+	manufacture_info(type, *this, nullptr);
+}
+
+FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initvals, cell_->name)
+{
+	cell = cell_;
+	manufacture_info(cell, *this, initvals);
 }
 
 FfData FfData::slice(const std::vector<int> &bits) {
diff --git a/kernel/ff.h b/kernel/ff.h
index d6cf99b9b..217658d35 100644
--- a/kernel/ff.h
+++ b/kernel/ff.h
@@ -78,31 +78,20 @@ YOSYS_NAMESPACE_BEGIN
 // - has_arst [does not correspond to a native cell, represented as dlatch with const D input]
 // - empty set [not a cell — will be emitted as a simple direct connection]
 
-struct FfData {
-	Module *module;
-	FfInitVals *initvals;
-	Cell *cell;
-	IdString name;
-	// The FF output.
-	SigSpec sig_q;
-	// The sync data input, present if has_clk or has_gclk.
-	SigSpec sig_d;
-	// The async data input, present if has_aload.
-	SigSpec sig_ad;
-	// The sync clock, present if has_clk.
-	SigSpec sig_clk;
-	// The clock enable, present if has_ce.
-	SigSpec sig_ce;
-	// The async load enable, present if has_aload.
-	SigSpec sig_aload;
-	// The async reset, preset if has_arst.
-	SigSpec sig_arst;
-	// The sync reset, preset if has_srst.
-	SigSpec sig_srst;
-	// The async clear (per-lane), present if has_sr.
-	SigSpec sig_clr;
-	// The async set (per-lane), present if has_sr.
-	SigSpec sig_set;
+struct FfTypeData {
+	FfTypeData(IdString type);
+	FfTypeData() {
+		has_clk = false;
+		has_gclk = false;
+		has_ce = false;
+		has_aload = false;
+		has_srst = false;
+		has_arst = false;
+		has_sr = false;
+		ce_over_srst = false;
+		is_fine = false;
+		is_anyinit = false;
+	}
 	// True if this is a clocked (edge-sensitive) flip-flop.
 	bool has_clk;
 	// True if this is a $ff, exclusive with every other has_*.
@@ -143,9 +132,38 @@ struct FfData {
 	bool pol_clr;
 	bool pol_set;
 	// The value loaded by sig_arst.
+	// Zero length if unknowable from just type
 	Const val_arst;
 	// The value loaded by sig_srst.
+	// Zero length if unknowable from just type
 	Const val_srst;
+};
+
+struct FfData : FfTypeData {
+	Module *module;
+	FfInitVals *initvals;
+	Cell *cell;
+	IdString name;
+	// The FF output.
+	SigSpec sig_q;
+	// The sync data input, present if has_clk or has_gclk.
+	SigSpec sig_d;
+	// The async data input, present if has_aload.
+	SigSpec sig_ad;
+	// The sync clock, present if has_clk.
+	SigSpec sig_clk;
+	// The clock enable, present if has_ce.
+	SigSpec sig_ce;
+	// The async load enable, present if has_aload.
+	SigSpec sig_aload;
+	// The async reset, preset if has_arst.
+	SigSpec sig_arst;
+	// The sync reset, preset if has_srst.
+	SigSpec sig_srst;
+	// The async clear (per-lane), present if has_sr.
+	SigSpec sig_clr;
+	// The async set (per-lane), present if has_sr.
+	SigSpec sig_set;
 	// The initial value at power-up.
 	Const val_init;
 	// The FF data width in bits.
@@ -154,16 +172,6 @@ struct FfData {
 
 	FfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {
 		width = 0;
-		has_clk = false;
-		has_gclk = false;
-		has_ce = false;
-		has_aload = false;
-		has_srst = false;
-		has_arst = false;
-		has_sr = false;
-		ce_over_srst = false;
-		is_fine = false;
-		is_anyinit = false;
 		pol_clk = false;
 		pol_aload = false;
 		pol_ce = false;
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 9bf615a7e..cb267e369 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -57,3 +57,5 @@ OBJS += passes/cmds/abstract.o
 OBJS += passes/cmds/test_select.o
 OBJS += passes/cmds/timeest.o
 OBJS += passes/cmds/linecoverage.o
+OBJS += passes/cmds/publish.o
+OBJS += passes/cmds/icell_liberty.o
diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc
new file mode 100644
index 000000000..83252ffb4
--- /dev/null
+++ b/passes/cmds/icell_liberty.cc
@@ -0,0 +1,217 @@
+#include "kernel/yosys.h"
+#include "kernel/celltypes.h"
+#include "kernel/ff.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct LibertyStubber {
+	CellTypes ct;
+	LibertyStubber() {
+		ct.setup();
+		ct.setup_internals_ff();
+	}
+	void liberty_prefix(std::ostream& f)
+	{
+		f << "/*\n";
+		f << stringf("\tModels interfaces of select Yosys internal cell.\n");
+		f << stringf("\tLikely contains INCORRECT POLARITIES.\n");
+		f << stringf("\tImpractical for any simulation, synthesis, or timing.\n");
+		f << stringf("\tIntended purely for SDC expansion.\n");
+		f << stringf("\tDo not microwave or tumble dry.\n");
+		f << stringf("\tGenerated by %s\n", yosys_maybe_version());
+		f << "*/\n";
+		f << "library (yosys) {\n";
+		f << "\tinput_threshold_pct_fall : 50;\n";
+		f << "\tinput_threshold_pct_rise : 50;\n";
+		f << "\toutput_threshold_pct_fall : 50;\n";
+		f << "\toutput_threshold_pct_rise : 50;\n";
+		f << "\tslew_lower_threshold_pct_fall : 1;\n";
+		f << "\tslew_lower_threshold_pct_rise : 1;\n";
+		f << "\tslew_upper_threshold_pct_fall : 99;\n";
+		f << "\tslew_upper_threshold_pct_rise : 99;\n";
+	}
+	void liberty_suffix(std::ostream& f)
+	{
+		f << "}\n";
+	}
+	struct LibertyItemizer {
+		std::ostream& f;
+		int indent;
+		LibertyItemizer(std::ostream& f) : f(f), indent(0) {};
+		void item(std::string key, std::string val)
+		{
+			f << std::string(indent, '\t') << key << " : \"" << val << "\";\n";
+		}
+	};
+	void liberty_flop(Module* base, Module* derived, std::ostream& f)
+	{
+		auto base_name = base->name.str().substr(1);
+		auto derived_name = derived->name.str().substr(1);
+
+		FfTypeData ffType(base_name);
+		LibertyItemizer i(f);
+
+		if (ffType.has_gclk) {
+			log_warning("Formal flip flop %s can't be modeled\n", base_name.c_str());
+			return;
+		}
+		if (ffType.has_ce) {
+			log_warning("DFFE %s can't be modeled\n", base_name.c_str());
+			return;
+		}
+
+		f << "\tcell (\"" << derived_name << "\") {\n";
+		auto& base_type = ct.cell_types[base_name];
+		i.indent = 3;
+		auto sorted_ports = derived->ports;
+		// Hack for CLK and C coming before Q does
+		auto cmp = [](IdString l, IdString r) { return l.str() < r.str(); };
+		std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
+		std::string clock_pin_name = "";
+		for (auto x : sorted_ports) {
+			std::string port_name = RTLIL::unescape_id(x);
+			bool is_input = base_type.inputs.count(x);
+			bool is_output = base_type.outputs.count(x);
+			f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
+			if (is_input && !is_output) {
+				i.item("direction", "input");
+			} else if (!is_input && is_output) {
+				i.item("direction", "output");
+			} else {
+				i.item("direction", "inout");
+			}
+			if (port_name == "CLK" || port_name == "C") {
+				i.item("clock", "true");
+				clock_pin_name = port_name;
+			}
+			if (port_name == "Q") {
+				i.item("function", "IQ");
+				f << "\t\t\ttiming () {\n";
+				i.indent++;
+				log_assert(clock_pin_name.size());
+				i.item("related_pin", clock_pin_name);
+				i.indent--;
+            	f << "\t\t\t}\n";
+			}
+			f << "\t\t}\n";
+		}
+
+		f << "\t\tff (\"IQ\",\"IQ_N\") {\n";
+		i.indent = 3;
+		// TODO polarities?
+		if (ffType.has_clk) {
+			auto pin = ffType.is_fine ? "C" : "CLK";
+			i.item("clocked_on", pin);
+		}
+		if (ffType.has_arst) {
+			auto meaning = (ffType.val_arst == State::S1) ? "preset" : "clear";
+			auto pin = ffType.is_fine ? "R" : "ARST";
+			i.item(meaning, pin);
+		}
+		auto next_state = ffType.has_ce ? "D & EN" : "D";
+		i.item("next_state", next_state);
+		f << "\t\t}\n";
+
+
+		// bool has_aload;
+		// bool has_srst;
+		// bool has_arst;
+		// bool has_sr;
+		f << "\t}\n";
+	}
+	void liberty_cell(Module* base, Module* derived, std::ostream& f)
+	{
+		auto base_name = base->name.str().substr(1);
+		auto derived_name = derived->name.str().substr(1);
+		if (!ct.cell_types.count(base_name)) {
+			log_debug("skip skeleton for %s\n", base_name.c_str());
+			return;
+		}
+
+		if (RTLIL::builtin_ff_cell_types().count(base_name))
+			return liberty_flop(base, derived, f);
+
+		auto& base_type = ct.cell_types[base_name];
+		f << "\tcell (\"" << derived_name << "\") {\n";
+		for (auto x : derived->ports) {
+			bool is_input = base_type.inputs.count(x);
+			bool is_output = base_type.outputs.count(x);
+			f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
+			if (is_input && !is_output) {
+				f << "\t\t\tdirection : input;\n";
+			} else if (!is_input && is_output) {
+				f << "\t\t\tdirection : output;\n";
+			} else {
+				f << "\t\t\tdirection : inout;\n";
+			}
+			f << "\t\t}\n";
+		}
+		f << "\t}\n";
+	}
+};
+
+struct IcellLiberty : Pass {
+	IcellLiberty() : Pass("icell_liberty", "write Liberty interfaces for used internal cells") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    icell_liberty <liberty_file>\n"); // TODO
+		log("\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *d) override
+	{
+		log_header(d, "Executing ICELL_LIBERTY pass.\n");
+
+		size_t argidx;
+		IdString naming_attr;
+		std::string liberty_filename;
+		std::ofstream* liberty_file = new std::ofstream;
+
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			break;
+		}
+		if (argidx < args.size())
+			liberty_filename = args[argidx++];
+		else
+			log_error("no Liberty filename specified\n");
+
+		// extra_args(args, argidx, d);
+
+		if (liberty_filename.size()) {
+			liberty_file->open(liberty_filename.c_str());
+			if (liberty_file->fail()) {
+				delete liberty_file;
+				log_error("Can't open file `%s' for writing: %s\n", liberty_filename.c_str(), strerror(errno));
+			}
+		}
+
+		pool<RTLIL::IdString> done;
+		LibertyStubber stubber = {};
+
+		if (liberty_file)
+			stubber.liberty_prefix(*liberty_file);
+
+		for (auto module : d->selected_modules()) {
+			for (auto cell : module->selected_cells()) {
+				Module *inst_module = d->module(cell->type);
+				if (!inst_module || !inst_module->get_blackbox_attribute())
+					continue;
+				Module *base = inst_module;
+				if (!done.count(base->name)) {
+					stubber.liberty_cell(base, base, *liberty_file);
+					done.insert(base->name);
+				}
+			}
+		}
+
+		if (liberty_file) {
+			stubber.liberty_suffix(*liberty_file);
+			delete liberty_file;
+		}
+	}
+} IcellLiberty;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/publish.cc b/passes/cmds/publish.cc
new file mode 100644
index 000000000..a5bc496f7
--- /dev/null
+++ b/passes/cmds/publish.cc
@@ -0,0 +1,40 @@
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PublishPass : public Pass {
+private:
+	static void publish(RTLIL::IdString& id) {
+		if (id.begins_with("$")) {
+			log_debug("publishing %s\n", id.c_str());
+			id = "\\" + id.str();
+			log_debug("published %s\n", id.c_str());
+		}
+	}
+public:
+	PublishPass() : Pass("publish", "publish private cell types") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    publish\n");
+		log("Makes all module names and cell types public by prefixing\n");
+		log("%% with \\.\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing PUBLISH pass. (make cell types public)\n");
+		extra_args(args, 1, design);
+		for (auto& [name, mod] : design->modules_) {
+			publish(name);
+			publish(mod->name);
+			for (auto* cell : mod->cells())
+				publish(cell->type);
+		}
+	}
+} PublishPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index e76d70a1a..1ae2c7ce8 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -2,6 +2,8 @@
 ifneq ($(SMALL),1)
 OBJS += techlibs/common/synth.o
 OBJS += techlibs/common/prep.o
+OBJS += techlibs/common/opensta.o
+OBJS += techlibs/common/sdc_expand.o
 endif
 
 GENFILES += techlibs/common/simlib_help.inc
diff --git a/techlibs/common/opensta.cc b/techlibs/common/opensta.cc
new file mode 100644
index 000000000..1b3571973
--- /dev/null
+++ b/techlibs/common/opensta.cc
@@ -0,0 +1,118 @@
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#if !defined(YOSYS_DISABLE_SPAWN)
+struct OpenstaPass : public Pass
+{
+	const char* default_sta_cmd = "sta";
+	OpenstaPass() : Pass("opensta", "run OpenSTA") { }
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    opensta [options]\n");
+		log("\n");
+		// TOOD
+		log("\n");
+		log("    -exe <command>\n");
+		log("        use <command> to run OpenSTA instead of \"%s\"\n", default_sta_cmd);
+		log("\n");
+		log("    -sdc-in <filename>\n");
+		log("        expand SDC input file <filename>\n");
+		log("\n");
+		log("    -sdc-out <filename>\n");
+		log("        expand SDC file to output file <filename>\n");
+		log("\n");
+		log("    -nocleanup\n");
+		log("\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		string run_from, run_to;
+		string opensta_exe = "sta";
+		string sdc_filename, sdc_expanded_filename;
+		string tempdir_name, script_filename;
+		string verilog_filename, liberty_filename;
+		bool cleanup = true;
+
+		log_header(design, "Executing OPENSTA pass.\n");
+		log_push();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-exe" && argidx+1 < args.size()) {
+				opensta_exe = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-sdc-in" && argidx+1 < args.size()) {
+				sdc_filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-sdc-out" && argidx+1 < args.size()) {
+				sdc_expanded_filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-verilog" && argidx+1 < args.size()) {
+				verilog_filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
+				liberty_filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-nocleanup") {
+				cleanup = false;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		if (cleanup)
+			tempdir_name = get_base_tmpdir() + "/";
+		else
+			tempdir_name = "_tmp_";
+		tempdir_name += proc_program_prefix() + "yosys-opensta-XXXXXX";
+		tempdir_name = make_temp_dir(tempdir_name);
+		script_filename = tempdir_name + "/opensta.tcl";
+		// script_filename
+
+		auto top_mod = design->top_module();
+		if (!top_mod)
+			log_error("Can't find top module in current design!\n");
+
+		std::ofstream f_script;
+		f_script.open(script_filename);
+
+		f_script << "read_verilog " << verilog_filename << "\n";
+		f_script << "read_lib " << liberty_filename << "\n";
+		f_script << "link_design " << RTLIL::unescape_id(top_mod->name) << "\n";
+		f_script << "read_sdc " << sdc_filename << "\n";
+		f_script << "write_sdc " << sdc_expanded_filename << "\n";
+		f_script.close();
+		std::string command = opensta_exe + " -exit " + script_filename; 
+		int ret = run_command(command);
+		if (ret)
+			log_error("OpenSTA return %d (error)\n", ret);
+		else
+			log("sdc_expanded_filename: %s\n", sdc_expanded_filename.c_str());
+
+		if (cleanup) {
+			log("Removing temp directory.\n");
+			remove_directory(tempdir_name);
+		}
+		log_pop();
+	}
+} OpenstaPass;
+#endif
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/common/sdc_expand.cc b/techlibs/common/sdc_expand.cc
new file mode 100644
index 000000000..1dcc8b9fa
--- /dev/null
+++ b/techlibs/common/sdc_expand.cc
@@ -0,0 +1,150 @@
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SdcexpandPass : public ScriptPass
+{
+	const char* default_sta_cmd = "sta";
+	SdcexpandPass() : ScriptPass("sdc_expand", "run OpenSTA") { }
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    sdc_expand [options]\n");
+		log("\n");
+		// TODO
+		log("\n");
+		log("    -exe <command>\n");
+		log("        use <command> to run OpenSTA instead of \"%s\"\n", default_sta_cmd);
+		log("\n");
+		log("    -sdc-in <filename>\n");
+		log("        expand SDC file <filename>\n");
+		log("\n");
+		log("    -nocleanup\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string opensta_exe, sdc_filename, sdc_expanded_filename;
+	bool cleanup;
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		string run_from, run_to;
+		cleanup = true;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-exe" && argidx+1 < args.size()) {
+				opensta_exe = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-sdc-in" && argidx+1 < args.size()) {
+				sdc_filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-sdc-out" && argidx+1 < args.size()) {
+				sdc_expanded_filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-nocleanup") {
+				cleanup = false;
+				continue;
+			}
+			// repetitive boring bit
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos) {
+					run_from = args[++argidx];
+					run_to = args[argidx];
+				} else {
+					run_from = args[++argidx].substr(0, pos);
+					run_to = args[argidx].substr(pos+1);
+				}
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		log_header(design, "Executing OPENSTA pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() override
+	{
+		std::string tempdir_name;
+		std::string liberty_path;
+		std::string verilog_path;
+
+		run("design -save pre_expand");
+		run("proc");
+		run("memory");
+		// run("dfflegalize -cell $dff");
+
+		std::string write_verilog_cmd = "write_verilog -norename -noexpr -attr2comment -defparam ";
+		if (help_mode) {
+			run(write_verilog_cmd + "<tmp_dir>/elaborated.v");
+		} else {
+			if (cleanup)
+				tempdir_name = get_base_tmpdir() + "/";
+			else
+				tempdir_name = "_tmp_";
+			tempdir_name += proc_program_prefix() + "yosys-sdc_expand-XXXXXX";
+			tempdir_name = make_temp_dir(tempdir_name);
+			verilog_path = tempdir_name + "/elaborated.v";
+			run(write_verilog_cmd + verilog_path);
+		}
+
+		run("read_verilog -setattr whitebox -defer -DSIMLIB_NOCHECKS +/simlib.v");
+		run("proc");
+		run("hierarchy -auto-top");
+		run("publish");
+
+		if (help_mode) {
+			run("icell_liberty <tmp_dir>/yosys.lib");
+		} else {
+			liberty_path = tempdir_name + "/yosys.lib";
+			run(stringf("icell_liberty %s", liberty_path.c_str()));
+		}
+
+		std::string opensta_pass_call = "opensta -exe ";
+		opensta_pass_call += help_mode ? "<exe>" : opensta_exe;
+		opensta_pass_call += " -sdc-in ";
+		opensta_pass_call += help_mode ? "<sdc-in>" : sdc_filename;
+		opensta_pass_call += " -sdc-out ";
+		opensta_pass_call += help_mode ? "<sdc-out>" : sdc_expanded_filename;
+		opensta_pass_call += " -verilog ";
+		opensta_pass_call += help_mode ? "<verilog>" : verilog_path;
+		opensta_pass_call += " -liberty ";
+		opensta_pass_call += help_mode ? "<tmp_dir>/yosys.lib" : liberty_path;
+		if (!cleanup)
+			opensta_pass_call += " -nocleanup";
+		run(opensta_pass_call.c_str());
+
+		if (!help_mode) {
+			if (cleanup) {
+				log("Removing temp directory.\n");
+				remove_directory(tempdir_name);
+			} else {
+				log("Keeping temp directory %s\n", tempdir_name.c_str());
+			}
+		}
+		run("design -load pre_expand");
+	}
+} SdcexpandPass;
+
+PRIVATE_NAMESPACE_END