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synth_*: no need to explicitly read +/abc9_model.v

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This commit is contained in:
Eddie Hung 2020-04-16 10:25:41 -07:00
parent 63246a5c0e
commit 8fbb55f4ab
4 changed files with 3 additions and 4 deletions
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1
techlibs/intel_alm/synth_intel_alm.cc
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@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("map_luts")) {
run("read_verilog -icells -specify -lib +/abc9_model.v");
run("abc9 -maxlut 6 -W 200");
run("techmap -map +/intel_alm/common/alm_map.v");
run("opt -fast");