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synth_*: no need to explicitly read +/abc9_model.v

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This commit is contained in:
Eddie Hung 2020-04-16 10:25:41 -07:00
parent 63246a5c0e
commit 8fbb55f4ab
4 changed files with 3 additions and 4 deletions
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2
techlibs/ice40/synth_ice40.cc
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@ -387,7 +387,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))