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synth_*: no need to explicitly read +/abc9_model.v

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This commit is contained in:
Eddie Hung 2020-04-16 10:25:41 -07:00
parent 63246a5c0e
commit 8fbb55f4ab
4 changed files with 3 additions and 4 deletions
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2
techlibs/ecp5/synth_ecp5.cc
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@ -338,7 +338,7 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap " + techmap_args);
if (abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
std::string abc9_opts;
if (nowidelut)
abc9_opts += " -maxlut 4";