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tests: remove -seq 1 from sat with -tempinduct where possible

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* When used with -tempinduct mode, -seq <N> causes assertions to be
  ignored in the first N steps. While this has uses for reset modelling,
  for these test cases it is unnecessary and could lead to failures
  slipping through uncaught
This commit is contained in:
George Rennie 2024-10-03 16:34:19 +02:00 • committed by Jannis Harder
parent 012ddc2f1e
commit 8fb3f88842
15 changed files with 16 additions and 16 deletions
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2
tests/verilog/atom_type_signedness.ys
View file

@ -16,4 +16,4 @@ endmodule
EOT
hierarchy; proc; opt; async2sync
select -module dut
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/int_types.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/mem_bounds.ys
View file

@ -4,4 +4,4 @@ flatten
opt -full
select -module top
async2sync
sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef
sat -verify -tempinduct -prove-asserts -show-all -enable_undef

2
tests/verilog/param_no_default.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/parameters_across_files.ys
View file

@ -18,4 +18,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/typedef_across_files.ys
View file

@ -21,4 +21,4 @@ proc
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/typedef_legacy_conflict.ys
View file

@ -35,4 +35,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/unbased_unsized.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/unbased_unsized_shift.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all