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Merge branch 'master' into krys/docs

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Fix failing verific tests
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Krystine Sherwin 2023-11-01 13:17:31 +13:00
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README.md
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@ -592,6 +592,8 @@ from SystemVerilog:
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
- Assignments within expressions are supported.
Building the documentation
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