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synth_analogdevices: update timing model and tests

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Lofty 2025-11-10 13:19:12 +00:00
parent 6ccd1da030
commit 8fad004fb8
27 changed files with 213 additions and 617 deletions
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tests/arch/analogdevices/asym_ram_sdp_write_wider.v
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@ -46,6 +46,7 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
(* ram_style="block" *)
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;