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Improved checking of internal cell conventions

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This commit is contained in:
Clifford Wolf 2014-02-08 19:13:49 +01:00
parent 7f52c18a22
commit 8f9c707a4c
1 changed files with 17 additions and 8 deletions
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25
kernel/rtlil.cc
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@ -331,11 +331,20 @@ namespace {
int param_bool(const char *name) int param_bool(const char *name)
{ {
int v = param(name); int v = param(name);
if (cell->parameters.at(name).bits.size() > 32)
error(__LINE__);
if (v != 0 && v != 1) if (v != 0 && v != 1)
error(__LINE__); error(__LINE__);
return v; return v;
} }
void param_bits(const char *name, int width)
{
param(name);
if (int(cell->parameters.at(name).bits.size()) != width)
error(__LINE__);
}
void port(const char *name, int width) void port(const char *name, int width)
{ {
if (cell->connections.count(name) == 0) if (cell->connections.count(name) == 0)
@ -541,7 +550,7 @@ namespace {
if (cell->type == "$adff") { if (cell->type == "$adff") {
param_bool("\\CLK_POLARITY"); param_bool("\\CLK_POLARITY");
param_bool("\\ARST_POLARITY"); param_bool("\\ARST_POLARITY");
param("\\ARST_VALUE"); param_bits("\\ARST_VALUE", param("\\WIDTH"));
port("\\CLK", 1); port("\\CLK", 1);
port("\\ARST", 1); port("\\ARST", 1);
port("\\D", param("\\WIDTH")); port("\\D", param("\\WIDTH"));
@ -567,9 +576,9 @@ namespace {
param("\\STATE_NUM"); param("\\STATE_NUM");
param("\\STATE_NUM_LOG2"); param("\\STATE_NUM_LOG2");
param("\\STATE_RST"); param("\\STATE_RST");
param("\\STATE_TABLE"); param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
param("\\TRANS_NUM"); param("\\TRANS_NUM");
param("\\TRANS_TABLE"); param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
port("\\CLK", 1); port("\\CLK", 1);
port("\\ARST", 1); port("\\ARST", 1);
port("\\CTRL_IN", param("\\CTRL_IN_WIDTH")); port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
@ -607,11 +616,11 @@ namespace {
param("\\MEMID"); param("\\MEMID");
param("\\SIZE"); param("\\SIZE");
param("\\OFFSET"); param("\\OFFSET");
param("\\RD_CLK_ENABLE"); param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
param("\\RD_CLK_POLARITY"); param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
param("\\RD_TRANSPARENT"); param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
param("\\WR_CLK_ENABLE"); param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
param("\\WR_CLK_POLARITY"); param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
port("\\RD_CLK", param("\\RD_PORTS")); port("\\RD_CLK", param("\\RD_PORTS"));
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));