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verilog: allow null gen-if then block

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This commit is contained in:
Zachary Snow 2020-05-04 20:22:16 -04:00
parent 584780d776
commit 8f9bba1bbf
3 changed files with 23 additions and 1 deletions
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7
frontends/verilog/verilog_parser.y
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@ -2533,7 +2533,12 @@ gen_stmt:
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
ast_stack.back()->children.push_back($3);
} gen_stmt_block opt_gen_else {
AstNode *block = new AstNode(AST_GENBLOCK);
ast_stack.back()->children.push_back(block);
ast_stack.push_back(block);
} gen_stmt_or_null {
ast_stack.pop_back();
} opt_gen_else {
SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
ast_stack.pop_back();
} |