mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Revert "write_json to not write contents (cells/wires) of whiteboxes"

Browse source 
This reverts commit 4ef03e19a8.
This commit is contained in:
Eddie Hung 2019-04-18 23:05:59 -07:00
parent 4ef03e19a8
commit 8f93999129
1 changed files with 56 additions and 59 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

115
backends/json/json.cc
View file

@ -130,75 +130,72 @@ struct JsonWriter
f << stringf(" }"); f << stringf(" }");
first = false; first = false;
} }
f << stringf("\n }"); f << stringf("\n },\n");
if (!module->get_blackbox_attribute()) { f << stringf(" \"cells\": {");
f << stringf(",\n \"cells\": {"); first = true;
first = true; for (auto c : module->cells()) {
for (auto c : module->cells()) { if (use_selection && !module->selected(c))
if (use_selection && !module->selected(c)) continue;
continue; f << stringf("%s\n", first ? "" : ",");
f << stringf("%s\n", first ? "" : ","); f << stringf(" %s: {\n", get_name(c->name).c_str());
f << stringf(" %s: {\n", get_name(c->name).c_str()); f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0"); f << stringf(" \"type\": %s,\n", get_name(c->type).c_str());
f << stringf(" \"type\": %s,\n", get_name(c->type).c_str()); if (aig_mode) {
if (aig_mode) { Aig aig(c);
Aig aig(c); if (!aig.name.empty()) {
if (!aig.name.empty()) { f << stringf(" \"model\": \"%s\",\n", aig.name.c_str());
f << stringf(" \"model\": \"%s\",\n", aig.name.c_str()); aig_models.insert(aig);
aig_models.insert(aig);
}
} }
f << stringf(" \"parameters\": {"); }
write_parameters(c->parameters); f << stringf(" \"parameters\": {");
f << stringf("\n },\n"); write_parameters(c->parameters);
f << stringf(" \"attributes\": {"); f << stringf("\n },\n");
write_parameters(c->attributes); f << stringf(" \"attributes\": {");
f << stringf("\n },\n"); write_parameters(c->attributes);
if (c->known()) { f << stringf("\n },\n");
f << stringf(" \"port_directions\": {"); if (c->known()) {
bool first2 = true; f << stringf(" \"port_directions\": {");
for (auto &conn : c->connections()) {
string direction = "output";
if (c->input(conn.first))
direction = c->output(conn.first) ? "inout" : "input";
f << stringf("%s\n", first2 ? "" : ",");
f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
first2 = false;
}
f << stringf("\n },\n");
}
f << stringf(" \"connections\": {");
bool first2 = true; bool first2 = true;
for (auto &conn : c->connections()) { for (auto &conn : c->connections()) {
string direction = "output";
if (c->input(conn.first))
direction = c->output(conn.first) ? "inout" : "input";
f << stringf("%s\n", first2 ? "" : ","); f << stringf("%s\n", first2 ? "" : ",");
f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str()); f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
first2 = false; first2 = false;
} }
f << stringf("\n }\n"); f << stringf("\n },\n");
f << stringf(" }");
first = false;
} }
f << stringf("\n },\n"); f << stringf(" \"connections\": {");
bool first2 = true;
f << stringf(" \"netnames\": {"); for (auto &conn : c->connections()) {
first = true; f << stringf("%s\n", first2 ? "" : ",");
for (auto w : module->wires()) { f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
if (use_selection && !module->selected(w)) first2 = false;
continue;
f << stringf("%s\n", first ? "" : ",");
f << stringf(" %s: {\n", get_name(w->name).c_str());
f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
f << stringf(" \"attributes\": {");
write_parameters(w->attributes);
f << stringf("\n }\n");
f << stringf(" }");
first = false;
} }
f << stringf("\n }"); f << stringf("\n }\n");
f << stringf(" }");
first = false;
} }
f << stringf("\n"); f << stringf("\n },\n");
f << stringf(" \"netnames\": {");
first = true;
for (auto w : module->wires()) {
if (use_selection && !module->selected(w))
continue;
f << stringf("%s\n", first ? "" : ",");
f << stringf(" %s: {\n", get_name(w->name).c_str());
f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
f << stringf(" \"attributes\": {");
write_parameters(w->attributes);
f << stringf("\n }\n");
f << stringf(" }");
first = false;
}
f << stringf("\n }\n");
f << stringf(" }"); f << stringf(" }");
} }