mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"

Browse source
This commit is contained in:
Clifford Wolf 2017-06-07 12:30:24 +02:00
parent 129984e115
commit 8f8baccfde
5 changed files with 61 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

7
frontends/ast/genrtlil.cc
View file

@ -1497,6 +1497,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
cell->parameters["\\WIDTH"] = width;
if (attributes.count("\\reg")) {
auto &attr = attributes.at("\\reg");
if (attr->type != AST_CONSTANT)
log_error("Attribute `reg' with non-constant value at %s:%d!\n", filename.c_str(), linenum);
cell->attributes["\\reg"] = attr->asAttrConst();
}
Wire *wire = current_module->addWire(myid + "_wire", width);
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
cell->setPort("\\Y", wire);