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fifo

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Miodrag Milanovic 2024-03-13 09:48:16 +01:00
parent 012f0e2952
commit 8f42d6dace
3 changed files with 513 additions and 198 deletions
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198
techlibs/nanoxplore/cells_bb.v
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@ -165,158 +165,6 @@ module NX_ECC(CKD, CHK, COR, ERR);
output ERR;
endmodule
(* blackbox *)
module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
input [17:0] I;
output [17:0] O;
input [5:0] RAI;
output [5:0] RAO;
input RCK;
output REQ;
input RRSTI;
output RRSTO;
input [5:0] WAI;
output [5:0] WAO;
input WCK;
input WE;
input WEA;
output WEQ;
input WRSTI;
output WRSTO;
parameter rck_edge = 1'b0;
parameter read_addr_inv = 6'b000000;
parameter use_read_arst = 1'b0;
parameter use_write_arst = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I17;
input I18;
input I19;
input I2;
input I20;
input I21;
input I22;
input I23;
input I24;
input I25;
input I26;
input I27;
input I28;
input I29;
input I3;
input I30;
input I31;
input I32;
input I33;
input I34;
input I35;
input I36;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O17;
output O18;
output O19;
output O2;
output O20;
output O21;
output O22;
output O23;
output O24;
output O25;
output O26;
output O27;
output O28;
output O29;
output O3;
output O30;
output O31;
output O32;
output O33;
output O34;
output O35;
output O36;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RAI1;
input RAI2;
input RAI3;
input RAI4;
input RAI5;
input RAI6;
input RAI7;
output RAO1;
output RAO2;
output RAO3;
output RAO4;
output RAO5;
output RAO6;
output RAO7;
input RCK;
output REQ1;
output REQ2;
input RRSTI;
output RRSTO;
input WAI1;
input WAI2;
input WAI3;
input WAI4;
input WAI5;
input WAI6;
input WAI7;
output WAO1;
output WAO2;
output WAO3;
output WAO4;
output WAO5;
output WAO6;
output WAO7;
input WCK;
input WE;
input WEA;
output WEQ1;
output WEQ2;
input WRSTI;
output WRSTO;
parameter mode = 0;
parameter rck_edge = 1'b0;
parameter read_addr_inv = 7'b0000000;
parameter use_read_arst = 1'b0;
parameter use_write_arst = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
@ -3395,52 +3243,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
parameter weakTermination = "";
endmodule
(* blackbox *)
module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
input [35:0] I;
output [35:0] O;
input [5:0] RAI;
output [5:0] RAO;
input RCK;
output REQ;
input RRSTI;
input [5:0] WAI;
output [5:0] WAO;
input WCK;
input WE;
input WEA;
output WEQ;
input WRSTI;
parameter rck_edge = 1'b0;
parameter read_addr_inv = 7'b0000000;
parameter use_read_arst = 1'b0;
parameter use_write_arst = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
input [17:0] I;
output [17:0] O;
input [6:0] RAI;
output [6:0] RAO;
input RCK;
output [1:0] REQ;
input RRSTI;
input [6:0] WAI;
output [6:0] WAO;
input WCK;
input WE;
input WEA;
output [1:0] WEQ;
input WRSTI;
parameter rck_edge = 1'b0;
parameter read_addr_inv = 7'b0000000;
parameter use_read_arst = 1'b0;
parameter use_write_arst = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module SMACC24x18_1DSP(clk, rst, A, B, Z);
input [23:0] A;