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Added $ff and $_FF_ cell types
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4a981a3bd8
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12 changed files with 118 additions and 19 deletions
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@ -388,6 +388,23 @@ void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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}
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void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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std::string gate_type = "$_FF_";
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\D", sig_d[i]);
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gate->setPort("\\Q", sig_q[i]);
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}
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}
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void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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@ -532,6 +549,7 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
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mappers["$slice"] = simplemap_slice;
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mappers["$concat"] = simplemap_concat;
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mappers["$sr"] = simplemap_sr;
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mappers["$ff"] = simplemap_ff;
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mappers["$dff"] = simplemap_dff;
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mappers["$dffe"] = simplemap_dffe;
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mappers["$dffsr"] = simplemap_dffsr;
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@ -569,7 +587,7 @@ struct SimplemapPass : public Pass {
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log(" $not, $pos, $and, $or, $xor, $xnor\n");
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log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
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log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
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log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
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log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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