mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-20 04:43:40 +00:00
Code Activity

Added $ff and $_FF_ cell types

Browse source
This commit is contained in:
Clifford Wolf 2016-10-12 01:18:39 +02:00
parent 4a981a3bd8
commit 8ebba8a35f
12 changed files with 118 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

38
passes/sat/miter.cc
View file

@ -312,18 +312,42 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
log_pop();
}
SigSpec or_signals;
SigSpec assert_signals, assume_signals;
vector<Cell*> cell_list = module->cells();
for (auto cell : cell_list) {
for (auto cell : cell_list)
{
if (!cell->type.in("$assert", "$assume"))
continue;
SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
if (cell->type == "$assert") {
SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
or_signals.append(module->And(NEW_ID, is_active, is_enabled));
module->remove(cell);
assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
} else {
assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
}
module->remove(cell);
}
module->addReduceOr(NEW_ID, or_signals, trigger);
if (assume_signals.empty())
{
module->addReduceOr(NEW_ID, assert_signals, trigger);
}
else
{
Wire *assume_q = module->addWire(NEW_ID);
assume_q->attributes["\\init"] = State::S1;
assume_signals.append(assume_q);
SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
SigSpec assume_ok = module->Not(NEW_ID, assume_nok);
module->addFf(NEW_ID, assume_ok, assume_q);
SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals);
module->addAnd(NEW_ID, assert_fail, assume_ok, trigger);
}
if (flag_flatten) {
log_push();