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Added $ff and $_FF_ cell types
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parent
4a981a3bd8
commit
8ebba8a35f
12 changed files with 118 additions and 19 deletions
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@ -315,6 +315,12 @@ struct BlifDumper
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continue;
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}
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if (!config->icells_mode && cell->type == "$_FF_") {
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f << stringf(".latch %s %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
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cstr_init(cell->getPort("\\Q")));
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continue;
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}
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if (!config->icells_mode && cell->type == "$_DFF_N_") {
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f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
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cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q")));
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@ -379,7 +379,7 @@ struct Smt2Worker
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return;
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}
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if (cell->type == "$_DFF_P_" || cell->type == "$_DFF_N_")
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if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
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{
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registers.insert(cell);
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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@ -407,7 +407,7 @@ struct Smt2Worker
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if (bvmode)
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{
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if (cell->type == "$dff")
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if (cell->type.in("$ff", "$dff"))
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{
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registers.insert(cell);
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
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@ -596,7 +596,7 @@ struct Smt2Worker
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pool<SigBit> reg_bits;
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for (auto cell : module->cells())
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if (cell->type.in("$_DFF_P_", "$_DFF_N_", "$dff")) {
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if (cell->type.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) {
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// not using sigmap -- we want the net directly at the dff output
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for (auto bit : cell->getPort("\\Q"))
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reg_bits.insert(bit);
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@ -674,14 +674,14 @@ struct Smt2Worker
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for (auto cell : this_regs)
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{
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if (cell->type == "$_DFF_P_" || cell->type == "$_DFF_N_")
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if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
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{
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std::string expr_d = get_bool(cell->getPort("\\D"));
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std::string expr_q = get_bool(cell->getPort("\\Q"), "next_state");
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trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q"))));
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}
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if (cell->type == "$dff")
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if (cell->type.in("$ff", "$dff"))
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{
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std::string expr_d = get_bv(cell->getPort("\\D"));
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std::string expr_q = get_bv(cell->getPort("\\Q"), "next_state");
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