multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues

kernel/python_wrappers.cc

@@ -31,79 +31,64 @@ namespace YOSYS_PYTHON {
 
 	struct Cell
 	{
-		Yosys::RTLIL::IdString name;
+		unsigned int id;
-		Yosys::RTLIL::IdString parent_name;
 
 		Cell(Yosys::RTLIL::Cell* ref)
 		{
-			this->name = ref->name;
+			this->id = ref->hashidx_;
-			this->parent_name = ref->module->name;
 		}
 	
-		Yosys::RTLIL::Cell* get_cpp_obj()
+		Yosys::RTLIL::Cell* get_cpp_obj() const
 		{
-			Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design();
+			return Yosys::RTLIL::Cell::get_all_cells()->at(this->id);
-			if(active_design == NULL)
-				return NULL;
-			if(active_design->modules_[this->parent_name] == NULL)
-				return NULL;
-			return active_design->modules_[this->parent_name]->cells_[this->name];
 		}
 	};
 
 	std::ostream &operator<<(std::ostream &ostr, const Cell &cell)
 	{
-		ostr << "Cell with name " << cell.name.c_str();
+		if(cell.get_cpp_obj() != NULL)
+			ostr << "Cell with name " << cell.get_cpp_obj()->name.c_str();
+		else
+			ostr << "deleted cell";
 		return ostr;
 	}
 
 	struct Wire
 	{
-		Yosys::RTLIL::IdString name;
+		unsigned int id;
-		Yosys::RTLIL::IdString parent_name;
 
 		Wire(Yosys::RTLIL::Wire* ref)
 		{
-			this->name = ref->name;
+			this->id = ref->hashidx_;
-			this->parent_name = ref->module->name;
 		}
 	
-		Yosys::RTLIL::Wire* get_cpp_obj()
+		Yosys::RTLIL::Wire* get_cpp_obj() const
 		{
-			Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design();
+			return Yosys::RTLIL::Wire::get_all_wires()->at(this->id);
-			if(active_design == NULL)
-				return NULL;
-			if(active_design->modules_[this->parent_name] == NULL)
-				return NULL;
-			return active_design->modules_[this->parent_name]->wires_[this->name];
 		}
 	};
 
 	std::ostream &operator<<(std::ostream &ostr, const Wire &wire)
 	{
-		ostr << "Wire with name " << wire.name.c_str();
+		if(wire.get_cpp_obj() != NULL)
+			ostr << "Wire with name " << wire.get_cpp_obj()->name.c_str();
+		else
+			ostr << "deleted wire";
 		return ostr;
 	}
 
 	struct Module
 	{
-		Yosys::RTLIL::IdString name;
+		unsigned int id;
-		unsigned int parent_hashid;
 
 		Module(Yosys::RTLIL::Module* ref)
 		{
-			this->name = ref->name;
+			this->id = ref->hashidx_;
-			this->parent_hashid = ref->design->hashidx_;
 		}
 
-		Yosys::RTLIL::Module* get_cpp_obj()
+		Yosys::RTLIL::Module* get_cpp_obj() const
 		{
-			Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design();
+			return Yosys::RTLIL::Module::get_all_modules()->at(this->id);
-			if(active_design == NULL)
-				return NULL;
-			if(active_design->hashidx_ != this->parent_hashid)
-				printf("Somehow the active design changed!\n");
-			return active_design->modules_[this->name];
 		}
 
 		boost::python::list get_cells()
@@ -135,7 +120,10 @@ namespace YOSYS_PYTHON {
 
 	std::ostream &operator<<(std::ostream &ostr, const Module &module)
 	{
-		ostr << "Module with name " << module.name.c_str();
+		if(module.get_cpp_obj() != NULL)
+			ostr << "Module with name " << module.get_cpp_obj()->name.c_str();
+		else
+			ostr << "deleted module";
 		return ostr;
 	}
 
@@ -150,21 +138,24 @@ namespace YOSYS_PYTHON {
 
 		Design()
 		{
-			Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design();
+			Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design();
-			if(active_design != NULL)
+			this->hashid = new_design->hashidx_;
-			{
+		}
-				printf("design is not null and has id %u\n", active_design->hashidx_);
+
-				this->hashid = active_design->hashidx_;
+		Yosys::RTLIL::Design* get_cpp_obj()
-			}
+		{
+			return Yosys::RTLIL::Design::get_all_designs()->at(hashid);
 		}
 
 		boost::python::list get_modules()
 		{
-			Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design();
+			Yosys::RTLIL::Design* cpp_design = get_cpp_obj();
 			boost::python::list result;
-			if(active_design == NULL)
+			if(cpp_design == NULL)
+			{
 				return result;
-			for(auto &mod_it : active_design->modules_)
+			}
+			for(auto &mod_it : cpp_design->modules_)
 			{
 				result.append(new Module(mod_it.second));
 			}
@@ -178,6 +169,16 @@ namespace YOSYS_PYTHON {
 		return ostr;
 	}
 
+	unsigned int get_active_design_id()
+	{
+		Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design();
+		if(active_design != NULL)
+		{
+			return active_design->hashidx_;
+		}
+		return 0;
+	}
+
 	BOOST_PYTHON_MODULE(libyosys)
 	{
 		using namespace boost::python;
@@ -207,6 +208,7 @@ namespace YOSYS_PYTHON {
 
 		def("yosys_setup",yosys_setup);
 		def("run",run);
+		def("get_active_design_id",get_active_design_id);
 		def("yosys_shutdown",yosys_shutdown);
 	}
 

kernel/rtlil.cc

@@ -358,6 +358,10 @@ RTLIL::Design::Design()
 
 	refcount_modules_ = 0;
 	selection_stack.push_back(RTLIL::Selection());
+
+#ifdef WITH_PYTHON
+	RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
+#endif
 }
 
 RTLIL::Design::~Design()
@@ -368,8 +372,19 @@ RTLIL::Design::~Design()
 		delete n;
 	for (auto n : verilog_globals)
 		delete n;
+#ifdef WITH_PYTHON
+	RTLIL::Design::get_all_designs()->erase(hashidx_);
+#endif
 }
 
+#ifdef WITH_PYTHON
+static std::map<unsigned int, RTLIL::Design*> *all_designs = new std::map<unsigned int, RTLIL::Design*>();
+std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
+{
+	return all_designs;
+}
+#endif
+
 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
 {
 	return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
@@ -625,6 +640,11 @@ RTLIL::Module::Module()
 	design = nullptr;
 	refcount_wires_ = 0;
 	refcount_cells_ = 0;
+
+#ifdef WITH_PYTHON
+	std::cout << "inserting module with name " << this->name.c_str() << "\n";
+	RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
+#endif
 }
 
 RTLIL::Module::~Module()
@@ -637,8 +657,19 @@ RTLIL::Module::~Module()
 		delete it->second;
 	for (auto it = processes.begin(); it != processes.end(); ++it)
 		delete it->second;
+#ifdef WITH_PYTHON
+	RTLIL::Module::get_all_modules()->erase(hashidx_);
+#endif
 }
 
+#ifdef WITH_PYTHON
+static std::map<unsigned int, RTLIL::Module*> *all_modules = new std::map<unsigned int, RTLIL::Module*>();
+std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
+{
+	return all_modules;
+}
+#endif
+
 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
 {
 	if (mayfail)
@@ -2187,8 +2218,20 @@ RTLIL::Wire::Wire()
 	port_input = false;
 	port_output = false;
 	upto = false;
+
+#ifdef WITH_PYTHON
+	RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
+#endif
 }
 
+#ifdef WITH_PYTHON
+static std::map<unsigned int, RTLIL::Wire*> *all_wires = new std::map<unsigned int, RTLIL::Wire*>();
+std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
+{
+	return all_wires;
+}
+#endif
+
 RTLIL::Memory::Memory()
 {
 	static unsigned int hashidx_count = 123456789;
@@ -2208,8 +2251,20 @@ RTLIL::Cell::Cell() : module(nullptr)
 
 	// log("#memtrace# %p\n", this);
 	memhasher();
+
+#ifdef WITH_PYTHON
+	RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
+#endif
 }
 
+#ifdef WITH_PYTHON
+static std::map<unsigned int, RTLIL::Cell*> *all_cells = new std::map<unsigned int, RTLIL::Cell*>();
+std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
+{
+	return all_cells;
+}
+#endif
+
 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
 {
 	return connections_.count(portname) != 0;

kernel/rtlil.h

@@ -874,6 +874,10 @@ struct RTLIL::Design
 		}
 	}
 
+#ifdef WITH_PYTHON
+	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
+#endif
+
 	std::vector<RTLIL::Module*> selected_modules() const;
 	std::vector<RTLIL::Module*> selected_whole_modules() const;
 	std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
@@ -1130,6 +1134,10 @@ public:
 	RTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = "");
 	RTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = "");
 	RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
+
+#ifdef WITH_PYTHON
+	static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
+#endif
 };
 
 struct RTLIL::Wire : public RTLIL::AttrObject
@@ -1152,6 +1160,10 @@ public:
 	RTLIL::IdString name;
 	int width, start_offset, port_id;
 	bool port_input, port_output, upto;
+
+#ifdef WITH_PYTHON
+	static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
+#endif
 };
 
 struct RTLIL::Memory : public RTLIL::AttrObject
@@ -1214,6 +1226,10 @@ public:
 	}
 
 	template<typename T> void rewrite_sigspecs(T &functor);
+
+#ifdef WITH_PYTHON
+	static std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);
+#endif
 };
 
 struct RTLIL::CaseRule