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https://github.com/YosysHQ/yosys
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Add "mutate -mode inv", various other mutate improvements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
ea8ee24140
commit
8e6b69d7bb
1 changed files with 213 additions and 99 deletions
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@ -34,10 +34,16 @@ struct mutate_opts_t {
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std::string mode;
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IdString module, cell, port;
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int bit = -1;
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IdString ctrl_name;
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int ctrl_width, ctrl_value;
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};
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void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, const mutate_t &entry)
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{
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if (!opts.mode.empty() && opts.mode != entry.mode)
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return;
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if (!opts.module.empty() && opts.module != entry.modname)
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return;
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@ -57,6 +63,183 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
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{
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}
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void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)
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{
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std::vector<mutate_t> database;
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for (auto module : design->selected_modules())
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{
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if (!opts.module.empty() && module->name != opts.module)
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continue;
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SigMap sigmap(module);
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for (auto wire : module->selected_wires())
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{
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for (SigBit bit : SigSpec(wire))
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{
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SigBit sigbit = sigmap(bit);
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if (bit.wire == nullptr || sigbit.wire == nullptr)
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continue;
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if (!bit.wire->port_id != !sigbit.wire->port_id) {
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if (bit.wire->port_id)
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sigmap.add(bit);
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continue;
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}
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if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
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if (bit.wire->name[0] == '\\')
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sigmap.add(bit);
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continue;
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}
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (!opts.cell.empty() && cell->name != opts.cell)
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continue;
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for (auto &conn : cell->connections())
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{
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for (int i = 0; i < GetSize(conn.second); i++) {
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mutate_t entry;
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entry.mode = "inv";
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entry.src = cell->get_src_attribute();
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entry.modname = module->name;
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entry.cellname = cell->name;
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entry.celltype = cell->type;
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entry.cellport = conn.first;
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entry.portbit = i;
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if (cell->output(conn.first)) {
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SigBit bit = sigmap(conn.second[i]);
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if (bit.wire && bit.wire->name[0] == '\\')
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entry.outsigbit = bit;
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}
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database_add(database, opts, entry);
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}
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}
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}
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}
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log("Raw database size: %d\n", GetSize(database));
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if (N != 0) {
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database_reduce(database, opts, N);
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log("Reduced database size: %d\n", GetSize(database));
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}
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std::ofstream fout;
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if (!filename.empty()) {
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fout.open(filename, std::ios::out | std::ios::trunc);
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if (!fout.is_open())
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log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
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}
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for (auto &entry : database) {
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string str = stringf("mutate -mode %s", entry.mode.c_str());
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if (!entry.modname.empty())
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str += stringf(" -module %s", log_id(entry.modname));
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if (!entry.cellname.empty())
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str += stringf(" -cell %s", log_id(entry.cellname));
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if (!entry.cellport.empty())
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str += stringf(" -port %s", log_id(entry.cellport));
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if (entry.portbit >= 0)
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str += stringf(" -bit %d", entry.portbit);
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if (entry.outsigbit.wire || !entry.src.empty()) {
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str += " #";
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if (!entry.src.empty())
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str += stringf(" %s", entry.src.c_str());
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if (entry.outsigbit.wire)
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str += stringf(" %s", log_signal(entry.outsigbit));
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}
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if (filename.empty())
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log("%s\n", str.c_str());
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else
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fout << str << std::endl;
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}
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}
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SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
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{
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Wire *ctrl_wire = module->wire(name);
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if (ctrl_wire == nullptr)
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{
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log("Adding ctrl port %s to module %s.\n", log_id(name), log_id(module));
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ctrl_wire = module->addWire(name, width);
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ctrl_wire->port_input = true;
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module->fixup_ports();
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for (auto mod : module->design->modules())
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for (auto cell : mod->cells())
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{
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if (cell->type != module->name)
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continue;
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SigSpec ctrl = mutate_ctrl_sig(mod, name, width);
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log("Connecting ctrl port to cell %s in module %s.\n", log_id(cell), log_id(mod));
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cell->setPort(name, ctrl);
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}
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}
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log_assert(GetSize(ctrl_wire) == width);
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return ctrl_wire;
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}
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SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts)
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{
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if (opts.ctrl_name.empty())
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return State::S1;
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SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width);
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return module->Eq(NEW_ID, sig, Const(opts.ctrl_value, GetSize(sig)));
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}
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SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec unchanged_sig, SigSpec changed_sig)
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{
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SigBit ctrl_bit = mutate_ctrl(module, opts);
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if (ctrl_bit == State::S0)
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return unchanged_sig;
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if (ctrl_bit == State::S1)
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return changed_sig;
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return module->Mux(NEW_ID, unchanged_sig, changed_sig, ctrl_bit);
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}
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void mutate_inv(Design *design, const mutate_opts_t &opts)
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{
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Module *module = design->module(opts.module);
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Cell *cell = module->cell(opts.cell);
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SigBit bit = cell->getPort(opts.port)[opts.bit];
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SigBit inbit, outbit;
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if (cell->input(opts.port))
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{
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log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.bit);
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SigBit outbit = module->Not(NEW_ID, bit);
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bit = mutate_ctrl_mux(module, opts, bit, outbit);
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}
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else
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{
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log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.bit);
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SigBit inbit = module->addWire(NEW_ID);
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SigBit outbit = module->Not(NEW_ID, inbit);
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module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
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bit = inbit;
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}
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SigSpec s = cell->getPort(opts.port);
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s[opts.bit] = bit;
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cell->setPort(opts.port, s);
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}
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struct MutatePass : public Pass {
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MutatePass() : Pass("mutate", "generate or apply design mutations") { }
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void help() YS_OVERRIDE
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@ -70,11 +253,29 @@ struct MutatePass : public Pass {
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log(" -o filename\n");
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log(" Write list to this file instead of console output\n");
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log("\n");
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log(" -mode name\n");
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log(" -module name\n");
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log(" -cell name\n");
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log(" -port name\n");
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log(" -bit int\n");
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log(" Filter list of mutation candidates to those matching\n");
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log(" the given parameters.\n");
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log("\n");
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log("\n");
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log(" mutate -mode MODE [options]\n");
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log("\n");
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log("Apply the given mutation.\n");
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log("\n");
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log(" -ctrl name width value\n");
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log(" Add a control signal with the given name and width. The mutation is\n");
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log(" activated if the control signal equals the given value.\n");
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log("\n");
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log(" -module name\n");
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log(" -cell name\n");
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log(" -port name\n");
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log(" -bit int\n");
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log(" Mutation parameters, as generated by 'mutate -list N'.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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@ -99,6 +300,12 @@ struct MutatePass : public Pass {
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opts.mode = args[++argidx];
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continue;
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}
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if (args[argidx] == "-ctrl" && argidx+3 < args.size()) {
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opts.ctrl_name = RTLIL::escape_id(args[++argidx]);
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opts.ctrl_width = atoi(args[++argidx].c_str());
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opts.ctrl_value = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-module" && argidx+1 < args.size()) {
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opts.module = RTLIL::escape_id(args[++argidx]);
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continue;
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@ -119,106 +326,13 @@ struct MutatePass : public Pass {
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}
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extra_args(args, argidx, design);
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if (N >= 0)
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{
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std::vector<mutate_t> database;
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for (auto module : design->selected_modules())
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{
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if (!opts.module.empty() && module->name != opts.module)
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continue;
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SigMap sigmap(module);
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for (auto wire : module->selected_wires())
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{
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for (SigBit bit : SigSpec(wire))
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{
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SigBit sigbit = sigmap(bit);
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if (bit.wire == nullptr || sigbit.wire == nullptr)
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continue;
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if (!bit.wire->port_id != !sigbit.wire->port_id) {
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if (bit.wire->port_id)
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sigmap.add(bit);
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continue;
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}
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if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
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if (bit.wire->name[0] == '\\')
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sigmap.add(bit);
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continue;
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}
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (!opts.cell.empty() && cell->name != opts.cell)
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continue;
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for (auto &conn : cell->connections())
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{
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for (int i = 0; i < GetSize(conn.second); i++) {
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mutate_t entry;
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entry.mode = "inv";
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entry.src = cell->get_src_attribute();
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entry.modname = module->name;
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entry.cellname = cell->name;
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entry.celltype = cell->type;
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entry.cellport = conn.first;
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entry.portbit = i;
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if (cell->output(conn.first)) {
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SigBit bit = sigmap(conn.second[i]);
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if (bit.wire && bit.wire->name[0] == '\\')
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entry.outsigbit = bit;
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}
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database_add(database, opts, entry);
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}
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}
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}
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}
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log("Raw database size: %d\n", GetSize(database));
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if (N != 0) {
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database_reduce(database, opts, N);
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log("Reduced database size: %d\n", GetSize(database));
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}
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std::ofstream fout;
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if (!filename.empty()) {
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fout.open(filename, std::ios::out | std::ios::trunc);
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if (!fout.is_open())
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log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
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}
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for (auto &entry : database) {
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string str = stringf("mutate -mode %s", entry.mode.c_str());
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if (!entry.modname.empty())
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str += stringf(" -module %s", log_id(entry.modname));
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if (!entry.cellname.empty())
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str += stringf(" -cell %s", log_id(entry.cellname));
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if (!entry.cellport.empty())
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str += stringf(" -port %s", log_id(entry.cellport));
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if (entry.portbit >= 0)
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str += stringf(" -bit %d", entry.portbit);
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if (entry.outsigbit.wire || !entry.src.empty()) {
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str += " #";
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if (!entry.src.empty())
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str += stringf(" %s", entry.src.c_str());
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if (entry.outsigbit.wire)
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str += stringf(" %s", log_signal(entry.outsigbit));
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}
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if (filename.empty())
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log("%s\n", str.c_str());
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else
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fout << str << std::endl;
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}
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if (N >= 0) {
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mutate_list(design, opts, filename, N);
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return;
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}
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if (opts.mode == "inv") {
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mutate_inv(design, opts);
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return;
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}
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