From fb864e91ee7ba47cc52a38024c353acec156b78a Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 14 Jan 2026 17:35:45 -0800 Subject: [PATCH 01/10] Add Design::run_pass() API for programmatic pass execution This commit adds a new run_pass() method to the RTLIL::Design class, providing a convenient API for executing Yosys passes programmatically. This is particularly useful for PyYosys users who want to run passes on a design object without needing to manually construct Pass::call() invocations. The method wraps Pass::call() with appropriate logging to maintain consistency with command-line pass execution. Example usage (from Python): design = ys.Design() # ... build or load design ... design.run_pass("hierarchy") design.run_pass("proc") design.run_pass("opt") Changes: - kernel/rtlil.h: Add run_pass() method declaration - kernel/rtlil.cc: Implement run_pass() method - tests/unit/kernel/test_design_run_pass.cc: Add unit tests --- kernel/rtlil.cc | 7 +++ kernel/rtlil.h | 3 ++ tests/unit/kernel/test_design_run_pass.cc | 59 +++++++++++++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 tests/unit/kernel/test_design_run_pass.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0103cabfb..357ac2c5a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1610,6 +1610,13 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial return result; } +void RTLIL::Design::run_pass(std::string command) +{ + log("\n-- Running command `%s' --\n", command.c_str()); + Pass::call(this, command); + log_flush(); +} + RTLIL::Module::Module() { static unsigned int hashidx_count = 123456789; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fe280c965..532aa20b4 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2031,6 +2031,9 @@ struct RTLIL::Design // returns all selected unboxed whole modules, warning the user if any // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } + + void run_pass(std::string command); + static std::map *get_all_designs(void); std::string to_rtlil_str(bool only_selected = true) const; diff --git a/tests/unit/kernel/test_design_run_pass.cc b/tests/unit/kernel/test_design_run_pass.cc new file mode 100644 index 000000000..0553f4eb2 --- /dev/null +++ b/tests/unit/kernel/test_design_run_pass.cc @@ -0,0 +1,59 @@ +#include +#include "kernel/rtlil.h" +#include "kernel/register.h" + +YOSYS_NAMESPACE_BEGIN + +class DesignRunPassTest : public testing::Test { +protected: + DesignRunPassTest() { + if (log_files.empty()) log_files.emplace_back(stdout); + } + virtual void SetUp() override { + IdString::ensure_prepopulated(); + } +}; + +TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully) +{ + // Create a design with a simple module + RTLIL::Design *design = new RTLIL::Design; + RTLIL::Module *module = new RTLIL::Module; + module->name = RTLIL::IdString("\\test_module"); + design->add(module); + + // Add a simple wire to the module + RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1); + wire->port_input = true; + wire->port_id = 1; + module->fixup_ports(); + + // Call run_pass with a simple pass + // We use "check" which is a simple pass that just validates the design + ASSERT_NO_THROW(design->run_pass("check")); + + // Verify the design still exists and has the module + EXPECT_EQ(design->modules().size(), 1); + EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr); + + delete design; +} + +TEST_F(DesignRunPassTest, RunPassWithHierarchy) +{ + // Create a design with a simple module + RTLIL::Design *design = new RTLIL::Design; + RTLIL::Module *module = new RTLIL::Module; + module->name = RTLIL::IdString("\\top"); + design->add(module); + + // Call run_pass with hierarchy pass + ASSERT_NO_THROW(design->run_pass("hierarchy")); + + // Verify the design still has the module + EXPECT_EQ(design->modules().size(), 1); + + delete design; +} + +YOSYS_NAMESPACE_END From cf511628b0dc3ec3cc3d372cab3f74f0208f79cc Mon Sep 17 00:00:00 2001 From: Natalia Date: Sun, 18 Jan 2026 02:11:09 -0800 Subject: [PATCH 02/10] modify generator for pyosys/wrappers.cc instead of headers --- kernel/rtlil.cc | 7 --- kernel/rtlil.h | 2 - pyosys/generator.py | 10 ++++ tests/pyosys/test_design_run_pass.py | 12 +++++ tests/unit/kernel/test_design_run_pass.cc | 59 ----------------------- 5 files changed, 22 insertions(+), 68 deletions(-) create mode 100644 tests/pyosys/test_design_run_pass.py delete mode 100644 tests/unit/kernel/test_design_run_pass.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 357ac2c5a..0103cabfb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1610,13 +1610,6 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial return result; } -void RTLIL::Design::run_pass(std::string command) -{ - log("\n-- Running command `%s' --\n", command.c_str()); - Pass::call(this, command); - log_flush(); -} - RTLIL::Module::Module() { static unsigned int hashidx_count = 123456789; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 532aa20b4..fea53081e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2032,8 +2032,6 @@ struct RTLIL::Design // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } - void run_pass(std::string command); - static std::map *get_all_designs(void); std::string to_rtlil_str(bool only_selected = true) const; diff --git a/pyosys/generator.py b/pyosys/generator.py index 7d4293abd..0dda98015 100644 --- a/pyosys/generator.py +++ b/pyosys/generator.py @@ -701,6 +701,16 @@ class PyosysWrapperGenerator(object): self.process_class_members(metadata, metadata, cls, basename) + if basename == "Design": + print( + '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(cmd, &s); })', + file=self.f, + ) + print( + '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(cmd, &s); })', + file=self.f, + ) + if expr := metadata.string_expr: print( f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})', diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py new file mode 100644 index 000000000..c9656fd7a --- /dev/null +++ b/tests/pyosys/test_design_run_pass.py @@ -0,0 +1,12 @@ +from pathlib import Path + +from pyosys import libyosys as ys + +__file_dir__ = Path(__file__).absolute().parent + +design = ys.Design() +design.run_pass( + ["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")] +) +design.run_pass("prep") +design.run_pass(["opt", "-full"]) diff --git a/tests/unit/kernel/test_design_run_pass.cc b/tests/unit/kernel/test_design_run_pass.cc deleted file mode 100644 index 0553f4eb2..000000000 --- a/tests/unit/kernel/test_design_run_pass.cc +++ /dev/null @@ -1,59 +0,0 @@ -#include -#include "kernel/rtlil.h" -#include "kernel/register.h" - -YOSYS_NAMESPACE_BEGIN - -class DesignRunPassTest : public testing::Test { -protected: - DesignRunPassTest() { - if (log_files.empty()) log_files.emplace_back(stdout); - } - virtual void SetUp() override { - IdString::ensure_prepopulated(); - } -}; - -TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully) -{ - // Create a design with a simple module - RTLIL::Design *design = new RTLIL::Design; - RTLIL::Module *module = new RTLIL::Module; - module->name = RTLIL::IdString("\\test_module"); - design->add(module); - - // Add a simple wire to the module - RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1); - wire->port_input = true; - wire->port_id = 1; - module->fixup_ports(); - - // Call run_pass with a simple pass - // We use "check" which is a simple pass that just validates the design - ASSERT_NO_THROW(design->run_pass("check")); - - // Verify the design still exists and has the module - EXPECT_EQ(design->modules().size(), 1); - EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr); - - delete design; -} - -TEST_F(DesignRunPassTest, RunPassWithHierarchy) -{ - // Create a design with a simple module - RTLIL::Design *design = new RTLIL::Design; - RTLIL::Module *module = new RTLIL::Module; - module->name = RTLIL::IdString("\\top"); - design->add(module); - - // Call run_pass with hierarchy pass - ASSERT_NO_THROW(design->run_pass("hierarchy")); - - // Verify the design still has the module - EXPECT_EQ(design->modules().size(), 1); - - delete design; -} - -YOSYS_NAMESPACE_END From b43c96b03da9a3d1a4ea358c6bc0920f5723f3e0 Mon Sep 17 00:00:00 2001 From: Natalia Date: Sun, 18 Jan 2026 02:24:36 -0800 Subject: [PATCH 03/10] fix pyosys Design.run_pass binding to use Pass::call signature --- pyosys/generator.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pyosys/generator.py b/pyosys/generator.py index 0dda98015..f1d429724 100644 --- a/pyosys/generator.py +++ b/pyosys/generator.py @@ -703,11 +703,11 @@ class PyosysWrapperGenerator(object): if basename == "Design": print( - '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(cmd, &s); })', + '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(&s, cmd); })', file=self.f, ) print( - '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(cmd, &s); })', + '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(&s, cmd); })', file=self.f, ) From 7439d2489e4e5bfedd987d0a7a306955cf451bf7 Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 29 Jan 2026 02:20:50 -0800 Subject: [PATCH 04/10] add assertion to run_pass test --- tests/pyosys/test_design_run_pass.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py index c9656fd7a..59316f269 100644 --- a/tests/pyosys/test_design_run_pass.py +++ b/tests/pyosys/test_design_run_pass.py @@ -3,10 +3,11 @@ from pathlib import Path from pyosys import libyosys as ys __file_dir__ = Path(__file__).absolute().parent +src = __file_dir__.parent / "simple" / "fiedler-cooley.v" design = ys.Design() -design.run_pass( - ["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")] -) -design.run_pass("prep") -design.run_pass(["opt", "-full"]) +design.run_pass(["read_verilog", str(src)]) +design.run_pass("hierarchy -top up3down5") +design.run_pass(["proc"]) +design.run_pass("opt -full") +design.run_pass("select -assert-mod-count 1 up3down5") From 61b1c3c75a56343dc494bfc514321615dad351d5 Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 29 Jan 2026 02:42:23 -0800 Subject: [PATCH 05/10] use run_pass in ecp5 add/sub test --- tests/pyosys/test_design_run_pass.py | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py index 59316f269..f0013577d 100644 --- a/tests/pyosys/test_design_run_pass.py +++ b/tests/pyosys/test_design_run_pass.py @@ -1,13 +1,20 @@ -from pathlib import Path - +from pathlib import Path from pyosys import libyosys as ys __file_dir__ = Path(__file__).absolute().parent -src = __file_dir__.parent / "simple" / "fiedler-cooley.v" +add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v" -design = ys.Design() -design.run_pass(["read_verilog", str(src)]) -design.run_pass("hierarchy -top up3down5") -design.run_pass(["proc"]) -design.run_pass("opt -full") -design.run_pass("select -assert-mod-count 1 up3down5") +base = ys.Design() +base.run_pass(["read_verilog", str(add_sub)]) +base.run_pass("hierarchy -top top") +base.run_pass(["proc"]) +base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5") + +postopt = ys.Design() +postopt.run_pass("design -load postopt") +postopt.run_pass(["cd", "top"]) +postopt.run_pass("select -assert-min 25 t:LUT4") +postopt.run_pass("select -assert-max 26 t:LUT4") +postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"]) +postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"]) +postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D") From 6af1b5b19c279c09319f3fa8c094df89c06e9f7e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 29 Jan 2026 18:47:12 +0000 Subject: [PATCH 06/10] Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal --- passes/techmap/abc.cc | 58 +++++++++++++++++++++++++++++++++---------- 1 file changed, 45 insertions(+), 13 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e73be611a..ae0f3e053 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1127,9 +1127,34 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module handle_loops(assign_map, module); } +static bool is_abc_prompt(const std::string &line, std::string &rest) { + size_t pos = 0; + while (true) { + // The prompt may not start at the start of the line, because + // ABC can output progress and maybe other data that isn't + // newline-terminated. + size_t start = line.find("abc ", pos); + if (start == std::string::npos) + return false; + pos = start + 4; + + size_t digits = 0; + while (pos + digits < line.size() && line[pos + digits] >= '0' && line[pos + digits] <= '9') + ++digits; + if (digits < 2) + return false; + if (line.substr(pos + digits, 2) == "> ") { + rest = line.substr(pos + digits + 2); + return true; + } + } +} + bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { std::string line; char buf[1024]; + bool seen_source_cmd = false; + bool seen_yosys_abc_done = false; while (true) { int ret = read(fd, buf, sizeof(buf) - 1); if (ret < 0) { @@ -1144,23 +1169,30 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { char *end = buf + ret; while (start < end) { char *p = static_cast(memchr(start, '\n', end - start)); - if (p == nullptr) { - break; + char *upto = p == nullptr ? end : p + 1; + line.append(start, upto - start); + start = upto; + + std::string rest; + bool is_prompt = is_abc_prompt(line, rest); + if (is_prompt && seen_source_cmd) { + // This is the first prompt after we sourced the script. + // We are done here. + // We won't have seen a newline yet since ABC is waiting at the prompt. + if (!seen_yosys_abc_done) + logs.log_error("ABC script did not complete successfully\n"); + return seen_yosys_abc_done; } - line.append(start, p + 1 - start); - if (line.substr(0, 14) == "YOSYS_ABC_DONE") { - // Ignore any leftover output, there should only be a prompt perhaps - return true; - } - // If ABC aborted the sourced script, it returns to the prompt and will - // never print YOSYS_ABC_DONE. Treat this as a failed run, not a hang. - if (line.substr(0, 7) == "Error: ") { - logs.log_error("ABC: %s", line.c_str()); - return false; + if (line.empty() || line[line.size() - 1] != '\n') { + // No newline yet, wait for more text + continue; } filt.next_line(line); + if (is_prompt && rest.substr(0, 7) == "source ") + seen_source_cmd = true; + if (line.substr(0, 14) == "YOSYS_ABC_DONE") + seen_yosys_abc_done = true; line.clear(); - start = p + 1; } line.append(start, end - start); } From 9c56c93632f0aca1a7ded76582ce41dea08d906a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 29 Jan 2026 18:47:42 +0000 Subject: [PATCH 07/10] Add missing newlines to some 'log_error's --- passes/techmap/abc.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index ae0f3e053..e9d02b85c 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -188,10 +188,10 @@ struct AbcProcess int status; int ret = waitpid(pid, &status, 0); if (ret != pid) { - log_error("waitpid(%d) failed", pid); + log_error("waitpid(%d) failed\n", pid); } if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { - log_error("ABC failed with status %X", status); + log_error("ABC failed with status %X\n", status); } if (from_child_pipe >= 0) close(from_child_pipe); @@ -203,12 +203,12 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { // fork()s. int to_child_pipe[2]; if (pipe2(to_child_pipe, O_CLOEXEC) != 0) { - logs.log_error("pipe failed"); + logs.log_error("pipe failed\n"); return std::nullopt; } int from_child_pipe[2]; if (pipe2(from_child_pipe, O_CLOEXEC) != 0) { - logs.log_error("pipe failed"); + logs.log_error("pipe failed\n"); return std::nullopt; } @@ -221,39 +221,39 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { posix_spawn_file_actions_t file_actions; if (posix_spawn_file_actions_init(&file_actions) != 0) { - logs.log_error("posix_spawn_file_actions_init failed"); + logs.log_error("posix_spawn_file_actions_init failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[1]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[0]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_adddup2(&file_actions, to_child_pipe[0], STDIN_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); + logs.log_error("posix_spawn_file_actions_adddup2 failed\n"); return std::nullopt; } if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDOUT_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); + logs.log_error("posix_spawn_file_actions_adddup2 failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[0]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[1]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } char arg1[] = "-s"; char* argv[] = { strdup(abc_exe), arg1, nullptr }; if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { - logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerror(errno)); + logs.log_error("posix_spawnp %s failed (errno=%s)\n", abc_exe, strerror(errno)); return std::nullopt; } free(argv[0]); @@ -1158,11 +1158,11 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { while (true) { int ret = read(fd, buf, sizeof(buf) - 1); if (ret < 0) { - logs.log_error("Failed to read from ABC, errno=%d", errno); + logs.log_error("Failed to read from ABC, errno=%d\n", errno); return false; } if (ret == 0) { - logs.log_error("ABC exited prematurely"); + logs.log_error("ABC exited prematurely\n"); return false; } char *start = buf; From b88d6588bc23fff3dd30a112b2646be288505c68 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 2 Feb 2026 11:25:57 +0100 Subject: [PATCH 08/10] Update ABC as per 2026-02-02 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 79010216c..734f64d5b 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 79010216cb87427dd7a0c8d38f156494221be006 +Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08 From 224549fb88fd4d2301d643aa1fb60958d631b93c Mon Sep 17 00:00:00 2001 From: Sean Luchen Date: Mon, 2 Feb 2026 15:26:03 -0800 Subject: [PATCH 09/10] Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. Signed-off-by: Sean Luchen --- frontends/verific/verific.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9f13eee23..6a1c81aa4 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3701,7 +3701,9 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; +#ifdef VERIFIC_VHDL_SUPPORT unsigned vhdl_mode = vhdl_file::UNDEFINED; +#endif bool is_formal = false; const char* filename = nullptr; From 153ddc0c84ce8de4896a7b11918199b8fc1022ac Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 3 Feb 2026 00:33:37 +0000 Subject: [PATCH 10/10] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e4ebf9887..92a854819 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.61+112 +YOSYS_VER := 0.61+129 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)