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aiger2: Support $bwmux
, comparison operators
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parent
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commit
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2 changed files with 76 additions and 8 deletions
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@ -83,6 +83,12 @@ assign name``_y2 = op name``_a2;
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`BIOP(xnor, ~^, 3, 3, 3)
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`BIOP(logic_and, &&, 4, 3, 1)
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`BIOP(logic_or, ||, 3, 3, 2)
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`BIOP(eq, ==, 3, 3, 1)
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`BIOP(ne, !=, 3, 3, 1)
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`BIOP(lt, <, 3, 3, 1)
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`BIOP(le, <=, 3, 3, 1)
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`BIOP(gt, >, 3, 3, 1)
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`BIOP(ge, >=, 3, 3, 1)
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`UNOP(not, ~, 3)
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`UNOP_REDUCE(logic_not, !, 3)
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`UNOP_REDUCE(reduce_and, &, 3)
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@ -97,6 +103,11 @@ wire [1:0] fa_a, fa_b, fa_c, fa_x, fa_y;
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\$fa #(
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.WIDTH(2)
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) fa(.A(fa_a), .B(fa_b), .C(fa_c), .X(fa_x), .Y(fa_y));
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wire [1:0] bwmux_a, bwmux_b, bwmux_s, bwmux_y;
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\$bwmux #(
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.WIDTH(2)
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) bwmux(.A(bwmux_a), .B(bwmux_b), .S(bwmux_s), .Y(bwmux_y));
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endmodule
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EOF
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@ -110,8 +121,8 @@ select -clear
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delete test
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read_aiger -module_name test aiger2_ops.aig
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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miter -equiv -flatten gold test miter
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sat -verify -prove trigger 0 miter
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miter -equiv -make_outcmp -flatten gold test miter
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sat -verify -show-ports -prove trigger 0 miter
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design -reset
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read_verilog -icells <<EOF
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