mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-29 23:43:16 +00:00
verilog: support recursive functions using ternary expressions
This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
This commit is contained in:
parent
9f7cd10c98
commit
8de2e863af
5 changed files with 195 additions and 19 deletions
|
@ -270,6 +270,9 @@ namespace AST
|
|||
bool is_simple_const_expr();
|
||||
std::string process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint);
|
||||
|
||||
bool is_recursive_function() const;
|
||||
std::pair<AstNode*, AstNode*> get_tern_choice();
|
||||
|
||||
// create a human-readable text representation of the AST (for debugging)
|
||||
void dumpAst(FILE *f, std::string indent) const;
|
||||
void dumpVlog(FILE *f, std::string indent) const;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue