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				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	updated to use get_src_attribute() and set_src_attribute().
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					 3 changed files with 7 additions and 10 deletions
				
			
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					@ -352,13 +352,12 @@ struct AlumaccWorker
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		{
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							{
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			auto n = it.second;
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								auto n = it.second;
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			auto cell = module->addCell(NEW_ID, "$macc");
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								auto cell = module->addCell(NEW_ID, "$macc");
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			auto src = n->cell->attributes["\\src"].decode_string();
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			macc_counter++;
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								macc_counter++;
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			log("  creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
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								log("  creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
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			if (!src.empty()) cell->attributes["\\src"] = src;
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								cell->set_src_attribute(n->cell->get_src_attribute());
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			n->macc.optimize(GetSize(n->y));
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								n->macc.optimize(GetSize(n->y));
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			n->macc.to_cell(cell);
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								n->macc.to_cell(cell);
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					@ -480,8 +479,8 @@ struct AlumaccWorker
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				log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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									log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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			log(": %s\n", log_id(n->alu_cell));
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								log(": %s\n", log_id(n->alu_cell));
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			src = n->cells.size() > 0 ? n->cells[0]->attributes["\\src"].decode_string() : "";
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								if (n->cells.size() > 0)
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			if (!src.empty()) n->alu_cell->attributes["\\src"] = src;
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									n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
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			n->alu_cell->setPort("\\A", n->a);
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								n->alu_cell->setPort("\\A", n->a);
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			n->alu_cell->setPort("\\B", n->b);
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								n->alu_cell->setPort("\\B", n->b);
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					@ -478,14 +478,14 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
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		auto cell_type = cell->type;
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							auto cell_type = cell->type;
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		auto cell_name = cell->name;
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							auto cell_name = cell->name;
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		auto cell_connections = cell->connections();
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							auto cell_connections = cell->connections();
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		std::string src = cell->attributes["\\src"].decode_string();
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							std::string src = cell->get_src_attribute();
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		module->remove(cell);
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							module->remove(cell);
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		cell_mapping &cm = cell_mappings[cell_type];
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							cell_mapping &cm = cell_mappings[cell_type];
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		RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
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							RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
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		if (!src.empty()) new_cell->attributes["\\src"] = src;
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							new_cell->set_src_attribute(src);
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		bool has_q = false, has_qn = false;
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							bool has_q = false, has_qn = false;
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		for (auto &port : cm.ports) {
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							for (auto &port : cm.ports) {
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					@ -172,7 +172,6 @@ struct TechmapWorker
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		std::string orig_cell_name;
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							std::string orig_cell_name;
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		pool<string> extra_src_attrs;
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							pool<string> extra_src_attrs;
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		std::string src = cell->attributes["\\src"].decode_string();
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		if (!flatten_mode)
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							if (!flatten_mode)
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		{
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							{
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					@ -341,7 +340,7 @@ struct TechmapWorker
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			RTLIL::Cell *c = module->addCell(c_name, it.second);
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								RTLIL::Cell *c = module->addCell(c_name, it.second);
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			design->select(module, c);
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								design->select(module, c);
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			if (!src.empty()) c->attributes["\\src"] = src;
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								c->set_src_attribute(cell->get_src_attribute());
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			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
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								if (!flatten_mode && c->type.substr(0, 2) == "\\$")
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				c->type = c->type.substr(1);
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									c->type = c->type.substr(1);
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					@ -467,7 +466,6 @@ struct TechmapWorker
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			log_assert(cell == module->cell(cell->name));
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								log_assert(cell == module->cell(cell->name));
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			bool mapped_cell = false;
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								bool mapped_cell = false;
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			std::string src       = cell->attributes["\\src"].decode_string();
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			std::string cell_type = cell->type.str();
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								std::string cell_type = cell->type.str();
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			if (in_recursion && cell_type.substr(0, 2) == "\\$")
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								if (in_recursion && cell_type.substr(0, 2) == "\\$")
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					@ -517,7 +515,7 @@ struct TechmapWorker
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								extmapper_module = extmapper_design->addModule(m_name);
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													extmapper_module = extmapper_design->addModule(m_name);
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								RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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													RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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								if (!src.empty()) extmapper_cell->attributes["\\src"] = src;
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													extmapper_cell->set_src_attribute(cell->get_src_attribute());
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								int port_counter = 1;
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													int port_counter = 1;
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								for (auto &c : extmapper_cell->connections_) {
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													for (auto &c : extmapper_cell->connections_) {
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