mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Added module->avail_parameters (for advanced techmap features)

Browse source
This commit is contained in:
Clifford Wolf 2013-11-24 20:29:07 +01:00
parent 4011d47646
commit 8dafecd34d
3 changed files with 14 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
frontends/ast/genrtlil.cc
View file

@ -805,7 +805,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_TASK: case AST_TASK:
case AST_FUNCTION: case AST_FUNCTION:
case AST_AUTOWIRE: case AST_AUTOWIRE:
case AST_PARAMETER:
case AST_LOCALPARAM: case AST_LOCALPARAM:
case AST_DEFPARAM: case AST_DEFPARAM:
case AST_GENVAR: case AST_GENVAR:
@ -814,6 +813,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENIF: case AST_GENIF:
break; break;
// remember the parameter, needed for example in techmap
case AST_PARAMETER:
current_module->avail_parameters.insert(str);
break;
// create an RTLIL::Wire for an AST_WIRE node // create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: { case AST_WIRE: {
if (current_module->wires.count(str) != 0) if (current_module->wires.count(str) != 0)

1
kernel/rtlil.h
View file

@ -257,6 +257,7 @@ struct RTLIL::Design {
struct RTLIL::Module { struct RTLIL::Module {
RTLIL::IdString name; RTLIL::IdString name;
std::set<RTLIL::IdString> avail_parameters;
std::map<RTLIL::IdString, RTLIL::Wire*> wires; std::map<RTLIL::IdString, RTLIL::Wire*> wires;
std::map<RTLIL::IdString, RTLIL::Memory*> memories; std::map<RTLIL::IdString, RTLIL::Memory*> memories;
std::map<RTLIL::IdString, RTLIL::Cell*> cells; std::map<RTLIL::IdString, RTLIL::Cell*> cells;

10
passes/techmap/techmap.cc
View file

@ -223,7 +223,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
continue; continue;
if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
continue; continue;
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0) if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
goto next_tpl; goto next_tpl;
parameters[conn.first] = conn.second.as_const(); parameters[conn.first] = conn.second.as_const();
} }
@ -232,6 +232,9 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
next_tpl: next_tpl:
continue; continue;
} }
if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
} }
std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters); std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
@ -475,7 +478,10 @@ struct TechmapPass : public Pass {
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap; std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
for (auto &it : map->modules) { for (auto &it : map->modules) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) { if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) {
celltypeMap[RTLIL::escape_id(it.second->attributes.at("\\techmap_celltype").str)].insert(it.first); char *p = strdup(it.second->attributes.at("\\techmap_celltype").str.c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
free(p);
} else } else
celltypeMap[it.first].insert(it.first); celltypeMap[it.first].insert(it.first);
} }