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Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-09-20 12:16:20 +02:00
parent c072e00a39
commit 8da0888bf6
2 changed files with 30 additions and 18 deletions

View file

@ -299,6 +299,7 @@ namespace AST
std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
RTLIL::Module *clone() const YS_OVERRIDE;
void loadconfig() const;
};
// this must be set by the language frontend before parsing the sources