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Added WORDS parameter to $meminit

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This commit is contained in:
Clifford Wolf 2015-07-31 10:40:09 +02:00
parent 3860c9a9f2
commit 8d6d5c30d9
6 changed files with 95 additions and 16 deletions
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32
passes/memory/memory_unpack.cc
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@ -77,6 +77,10 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
}
Const initval = memory->parameters.at("\\INIT");
RTLIL::Cell *last_init_cell = nullptr;
SigSpec last_init_data;
int last_init_addr;
for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) {
Const val = initval.extract(i, mem->width, State::Sx);
for (auto bit : val.bits)
@ -84,15 +88,29 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
goto found_non_undef_initval;
continue;
found_non_undef_initval:
RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
cell->parameters["\\MEMID"] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
cell->parameters["\\PRIORITY"] = i/mem->width;
cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
cell->setPort("\\DATA", val);
if (last_init_cell && last_init_addr+1 == i/mem->width) {
last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1;
last_init_data.append(val);
last_init_addr++;
} else {
if (last_init_cell)
last_init_cell->setPort("\\DATA", last_init_data);
RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
cell->parameters["\\MEMID"] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
cell->parameters["\\WORDS"] = 1;
cell->parameters["\\PRIORITY"] = i/mem->width;
cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
last_init_cell = cell;
last_init_addr = i/mem->width;
last_init_data = val;
}
}
if (last_init_cell)
last_init_cell->setPort("\\DATA", last_init_data);
module->remove(memory);
}