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Refactoring of memory_bram and xilinx brams

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This commit is contained in:
Clifford Wolf 2015-01-18 19:05:29 +01:00
parent 694cc01f1d
commit 8d295730e5
6 changed files with 496 additions and 704 deletions
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116
techlibs/xilinx/brams.txt
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@ -1,133 +1,67 @@
bram $__XILINX_RAMB36_SDP72
bram $__XILINX_RAMB36_SDP
abits 9
dbits 72
groups 2
ports 1 1
wrmode 0 1
enable 0 8
transp 2 0
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_SDP36
bram $__XILINX_RAMB18_SDP
abits 9
dbits 36
groups 2
ports 1 1
wrmode 0 1
enable 0 4
transp 2 0
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP18
abits 10
dbits 18
bram $__XILINX_RAMB18_TDP
abits 10 @a10d18
dbits 18 @a10d18
abits 11 @a11d9
dbits 9 @a11d9
abits 12 @a12d4
dbits 4 @a12d4
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 0 1
enable 0 2
transp 2 0
enable 0 2 @a10d18
enable 0 1 @a11d9 @a12d4 @a13d2 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP9
abits 11
dbits 9
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP4
abits 12
dbits 4
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP2
abits 13
dbits 2
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP1
abits 14
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
match $__XILINX_RAMB36_SDP72
match $__XILINX_RAMB36_SDP
min bits 4096
min efficiency 5
shuffle_enable 8
shuffle_enable B
or_next_if_better
endmatch
match $__XILINX_RAMB18_SDP36
match $__XILINX_RAMB18_SDP
min bits 4096
min efficiency 5
shuffle_enable 4
shuffle_enable B
or_next_if_better
endmatch
match $__XILINX_RAMB18_TDP18
match $__XILINX_RAMB18_TDP
min bits 4096
min efficiency 5
shuffle_enable 2
or_next_if_better
shuffle_enable B
make_transp
endmatch
match $__XILINX_RAMB18_TDP9
min bits 4096
min efficiency 5
shuffle_enable 2
or_next_if_better
endmatch
match $__XILINX_RAMB18_TDP4
min bits 4096
min efficiency 5
shuffle_enable 2
or_next_if_better
endmatch
match $__XILINX_RAMB18_TDP2
min bits 4096
min efficiency 5
shuffle_enable 2
or_next_if_better
endmatch
match $__XILINX_RAMB18_TDP1
min bits 4096
min efficiency 5
shuffle_enable 2
endmatch