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https://github.com/YosysHQ/yosys
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commit
8d22f6d7e1
28 changed files with 1174 additions and 51 deletions
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@ -3143,9 +3143,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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if (verific_opt) {
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log(" Optimizing netlist for %s.\n", it->first.c_str());
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// log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
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// nl->InferClockEnableMux();
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log(" Running post-elaboration for %s.\n", it->first.c_str());
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nl->PostElaborationProcess();
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@ -3864,14 +3861,17 @@ struct VerificPass : public Pass {
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{
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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unsigned verilog_mode = veri_file::UNDEFINED;
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#ifdef VERIFIC_VHDL_SUPPORT
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unsigned vhdl_mode = vhdl_file::UNDEFINED;
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bool is_formal = false;
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#endif
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bool is_formal = false;
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#else
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
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#endif
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#ifdef VERIFIC_VHDL_SUPPORT
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unsigned vhdl_mode = vhdl_file::UNDEFINED;
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#endif
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#endif
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const char* filename = nullptr;
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