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proc_dff: fix missing polarity parameters for $dffsr, add another fallback
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0d85044f6a
commit
8cf422a823
1 changed files with 8 additions and 2 deletions
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@ -169,8 +169,12 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
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}
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}
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log_assert(set_pol != std::nullopt);
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log_assert(reset_pol != std::nullopt);
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if (set_pol == std::nullopt || reset_pol == std::nullopt) {
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// set or reset never used, falling back to mux tree
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gen_dffsr_complex(mod, sigs, clk_polarity, async_rules, proc);
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return;
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}
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struct Builder {
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using BitControl = std::pair<std::optional<SigBit>, std::optional<SigBit>>;
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@ -280,6 +284,8 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
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RTLIL::Cell *cell = mod->addDffsr(sstr.str(), sigs.clk, sig_sr_set, sig_sr_clr, sigs.d, sigs.q, clk_polarity);
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cell->attributes = proc->attributes;
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cell->setParam(ID::SET_POLARITY, Const(*set_pol, 1));
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cell->setParam(ID::CLR_POLARITY, Const(*reset_pol, 1));
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log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
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cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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