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Merge pull request #2179 from splhack/static-cast

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Support SystemVerilog Static Cast
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clairexen 2020-07-01 16:40:20 +02:00 • committed by GitHub
commit 8ce4f8790e
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8
frontends/ast/simplify.cc
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@ -950,6 +950,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
case AST_TO_SIGNED:
case AST_TO_UNSIGNED:
case AST_SELFSZ:
case AST_CAST_SIZE:
case AST_CONCAT:
case AST_REPLICATE:
case AST_REDUCE_AND:
@ -3487,6 +3488,13 @@ replace_fcall_later:;
}
}
break;
case AST_CAST_SIZE:
if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) {
int width = children[0]->bitsAsConst().as_int();
RTLIL::Const val = children[1]->bitsAsConst(width);
newNode = mkconst_bits(val.bits, children[1]->is_signed);
}
break;
case AST_CONCAT:
string_op = !children.empty();
for (auto it = children.begin(); it != children.end(); it++) {