mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

ecp5: TRELLIS_FF bypass path only in async mode

Browse source
This commit is contained in:
Eddie Hung 2020-04-21 17:04:26 -07:00
parent 7146c0339e
commit 8cda29137e
1 changed files with 8 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
techlibs/ecp5/cells_sim.v
View file

@ -363,11 +363,11 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
$setup(CE, negedge CLK, 0); $setup(CE, negedge CLK, 0);
$setup(LSR, negedge CLK, 0); $setup(LSR, negedge CLK, 0);
`ifndef YOSYS `ifndef YOSYS
if (muxlsr) (negedge CLK => (Q : srval)) = 0; if (SRMODE == "ASYNC" && muxlsr) (negedge CLK => (Q : srval)) = 0;
`else `else
if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's // but for facilitating a bypass box, let's pretend it's
// a simple path // a simple path
`endif `endif
if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0; if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0;
endspecify endspecify
@ -377,11 +377,11 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
$setup(CE, posedge CLK, 0); $setup(CE, posedge CLK, 0);
$setup(LSR, posedge CLK, 0); $setup(LSR, posedge CLK, 0);
`ifndef YOSYS `ifndef YOSYS
if (muxlsr) (posedge CLK => (Q : srval)) = 0; if (SRMODE == "ASYNC" && muxlsr) (posedge CLK => (Q : srval)) = 0;
`else `else
if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's // but for facilitating a bypass box, let's pretend it's
// a simple path // a simple path
`endif `endif
if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0; if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0;
endspecify endspecify