From 8cda29137e0e1c19e1115211ee695681bc901030 Mon Sep 17 00:00:00 2001 From: Eddie Hung <eddie@fpgeh.com> Date: Tue, 21 Apr 2020 17:04:26 -0700 Subject: [PATCH] ecp5: TRELLIS_FF bypass path only in async mode --- techlibs/ecp5/cells_sim.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 6f37823e4..357fd9173 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -363,11 +363,11 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); $setup(CE, negedge CLK, 0); $setup(LSR, negedge CLK, 0); `ifndef YOSYS - if (muxlsr) (negedge CLK => (Q : srval)) = 0; + if (SRMODE == "ASYNC" && muxlsr) (negedge CLK => (Q : srval)) = 0; `else - if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path + if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path `endif if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0; endspecify @@ -377,11 +377,11 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); $setup(CE, posedge CLK, 0); $setup(LSR, posedge CLK, 0); `ifndef YOSYS - if (muxlsr) (posedge CLK => (Q : srval)) = 0; + if (SRMODE == "ASYNC" && muxlsr) (posedge CLK => (Q : srval)) = 0; `else - if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path + if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path `endif if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0; endspecify