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intel_alm: drop quartus support
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dd2195543b
commit
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21 changed files with 18 additions and 1190 deletions
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@ -9,8 +9,6 @@ cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL9X9
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select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
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# Cyclone 10 GX does not have 9x9 multipliers.
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
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@ -23,18 +21,6 @@ cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL18X18
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select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL18X18
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select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
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@ -47,14 +33,3 @@ cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL27X27
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select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL27X27
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select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
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