mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-09 04:31:25 +00:00
intel_alm: drop quartus support
This commit is contained in:
parent
dd2195543b
commit
8cc9aa7fc6
21 changed files with 18 additions and 1190 deletions
|
@ -10,16 +10,3 @@ select -assert-count 6 t:MISTRAL_ALUT2
|
|||
select -assert-count 2 t:MISTRAL_ALUT4
|
||||
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/logic.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:MISTRAL_NOT
|
||||
select -assert-count 6 t:MISTRAL_ALUT2
|
||||
select -assert-count 2 t:MISTRAL_ALUT4
|
||||
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
|
Loading…
Add table
Add a link
Reference in a new issue