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intel_alm: drop quartus support
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dd2195543b
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21 changed files with 18 additions and 1190 deletions
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@ -7,17 +7,6 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dff
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proc
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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@ -28,16 +17,5 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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