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intel_alm: drop quartus support

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This commit is contained in:
Lofty 2024-05-03 11:16:34 +01:00
parent dd2195543b
commit 8cc9aa7fc6
21 changed files with 18 additions and 1190 deletions
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32
techlibs/intel_alm/common/dff_sim.v
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@ -77,38 +77,6 @@ specify
if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
`endif
`ifdef arriav
specify
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 470;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 633;
if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 439;
$setup(DATAIN, posedge CLK, /* -170 */ 0);
$setup(ENA, posedge CLK, /* -170 */ 0);
$setup(SCLR, posedge CLK, /* -170 */ 0);
$setup(SLOAD, posedge CLK, /* -170 */ 0);
$setup(SDATA, posedge CLK, /* -170 */ 0);
if (ACLR === 1'b0) (ACLR => Q) = 215;
endspecify
`endif
`ifdef cyclone10gx
specify
// TODO (long-term): investigate these numbers.
// It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
$setup(DATAIN, posedge CLK, 268);
$setup(ENA, posedge CLK, 268);
$setup(SCLR, posedge CLK, 268);
$setup(SLOAD, posedge CLK, 268);
$setup(SDATA, posedge CLK, 268);
if (ACLR === 1'b0) (ACLR => Q) = 0;
endspecify
`endif
initial begin
// Altera flops initialise to zero.