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Make SigSpec conversion to vector of SigChunk use chunks iterator
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4672127610
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2 changed files with 9 additions and 1 deletions
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@ -5899,6 +5899,14 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R
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return true;
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return true;
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}
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}
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RTLIL::SigSpec::operator std::vector<RTLIL::SigChunk>() const
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{
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std::vector<RTLIL::SigChunk> result;
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for (const RTLIL::SigChunk &c : chunks())
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result.push_back(c);
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return result;
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}
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RTLIL::CaseRule::~CaseRule()
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RTLIL::CaseRule::~CaseRule()
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{
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{
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for (auto it = switches.begin(); it != switches.end(); it++)
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for (auto it = switches.begin(); it != switches.end(); it++)
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@ -1473,7 +1473,7 @@ public:
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static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
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static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
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static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
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static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
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operator std::vector<RTLIL::SigChunk>() const { pack(); return chunks_; }
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operator std::vector<RTLIL::SigChunk>() const;
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
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const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
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